Lines Matching refs:RT
704 equal the RT field. */
735 instruction or the RT field in a D, DS, X, XFX or XO form
738 #define RT RS
742 /* The RS and RT fields of the DS form stq instruction, which have
1395 equal the RT field. */
1763 /* An X_MASK with the RT field fixed. */
1775 /* An X_MASK with the RT and RA fields fixed. */
2063 { "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2064 { "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2065 { "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2066 { "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2067 { "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2068 { "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2069 { "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2070 { "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2071 { "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2072 { "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2073 { "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2074 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2075 { "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2076 { "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2077 { "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2078 { "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2079 { "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2080 { "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2081 { "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2082 { "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2083 { "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2084 { "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2085 { "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2086 { "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2087 { "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2088 { "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2089 { "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2090 { "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2091 { "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2092 { "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2093 { "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2094 { "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2095 { "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2096 { "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2097 { "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2098 { "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2099 { "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2100 { "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2101 { "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2102 { "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2103 { "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2104 { "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2105 { "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2106 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2107 { "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2108 { "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2109 { "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2110 { "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2111 { "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2112 { "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2113 { "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2114 { "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2115 { "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2116 { "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2117 { "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2118 { "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2119 { "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2120 { "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2121 { "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2122 { "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2123 { "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2124 { "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2125 { "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2126 { "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2127 { "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2128 { "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2129 { "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2130 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2131 { "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2132 { "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2133 { "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2134 { "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2135 { "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2136 { "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2137 { "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2138 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2139 { "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2140 { "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2141 { "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2142 { "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2143 { "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2144 { "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2145 { "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2146 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2588 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2589 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2591 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2592 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2594 { "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2611 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2612 { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2613 { "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2615 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2616 { "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2617 { "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2619 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2620 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2621 { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } },
2622 { "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } },
2623 { "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2624 { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } },
2626 { "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2627 { "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
2628 { "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } },
2629 { "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } },
2630 { "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } },
3436 { "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3437 { "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3438 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3439 { "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3440 { "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3441 { "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3442 { "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3443 { "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3444 { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
3445 { "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3446 { "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3447 { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3449 { "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3450 { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3452 { "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3453 { "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3454 { "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3455 { "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3456 { "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3457 { "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3458 { "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3459 { "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3461 { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3462 { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3464 { "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3465 { "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3466 { "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3467 { "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
3469 { "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } },
3470 { "mfcr", X(31,19), XRARB_MASK, NOPOWER4 | COM, { RT } },
3471 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3473 { "lwarx", X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH } },
3475 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
3480 { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
3481 { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3504 { "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } },
3511 { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3512 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3513 { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3514 { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3515 { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3516 { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3517 { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3518 { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3520 { "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3524 { "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3525 { "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3529 { "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3553 { "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3554 { "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3556 { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3557 { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3564 { "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3566 { "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } },
3571 { "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
3575 { "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } },
3577 { "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
3578 { "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
3579 { "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3580 { "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3582 { "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3583 { "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3584 { "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3585 { "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3591 { "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3600 { "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } },
3602 { "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3608 { "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3609 { "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3610 { "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3611 { "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3612 { "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3613 { "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3614 { "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3615 { "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3617 { "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3618 { "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3619 { "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3620 { "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3621 { "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3622 { "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3623 { "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3624 { "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3672 { "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3673 { "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3674 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3675 { "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3676 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3677 { "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3678 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3679 { "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3681 { "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3682 { "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3683 { "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3684 { "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3685 { "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3686 { "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3687 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3688 { "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3706 { "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3707 { "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3708 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3709 { "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3710 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3711 { "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3712 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3713 { "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3715 { "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3716 { "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3717 { "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3718 { "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3720 { "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3721 { "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3722 { "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3723 { "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3724 { "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3725 { "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3726 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3727 { "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3729 { "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3730 { "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3731 { "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3732 { "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3733 { "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3734 { "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3735 { "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3736 { "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3755 { "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3756 { "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3757 { "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3758 { "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3760 { "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3761 { "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3762 { "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3763 { "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3764 { "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3765 { "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3766 { "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3767 { "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3771 { "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3773 { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3774 { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3778 { "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
3785 { "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } },
3790 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3792 { "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3797 { "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3799 { "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3800 { "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3801 { "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3802 { "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3803 { "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3804 { "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3805 { "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3806 { "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3807 { "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3808 { "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3809 { "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3810 { "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3811 { "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
3812 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3813 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3814 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3815 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3816 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3817 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3818 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3819 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3820 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3821 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3822 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3823 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3824 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3825 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3826 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3827 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3828 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3829 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3830 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3831 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
3832 { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
3833 { "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
3835 { "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3836 { "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3837 { "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3838 { "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3840 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3842 { "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3843 { "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3844 { "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3845 { "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3846 { "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
3847 { "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
3848 { "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3849 { "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3850 { "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3851 { "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3852 { "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
3853 { "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3854 { "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3855 { "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3856 { "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
3857 { "mfcfar", XSPR(31,339,28), XSPR_MASK, POWER6, { RT } },
3858 { "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
3859 { "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3860 { "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
3861 { "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
3862 { "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
3863 { "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
3864 { "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
3865 { "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
3866 { "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
3867 { "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3868 { "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3869 { "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3870 { "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3871 { "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3872 { "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3873 { "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3874 { "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3875 { "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3876 { "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3877 { "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3878 { "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3879 { "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3880 { "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3881 { "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3882 { "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3883 { "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3884 { "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
3885 { "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
3886 { "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3887 { "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
3888 { "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3889 { "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
3890 { "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
3891 { "mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, { RT, SPRG } },
3892 { "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3893 { "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3894 { "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3895 { "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
3896 { "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405 | BOOKE, { RT } },
3897 { "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405 | BOOKE, { RT } },
3898 { "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405 | BOOKE, { RT } },
3899 { "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405 | BOOKE, { RT } },
3900 { "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3901 { "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3902 { "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
3903 { "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3904 { "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
3905 { "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
3906 { "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
3907 { "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
3908 { "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
3909 { "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
3910 { "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
3911 { "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
3912 { "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
3913 { "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
3914 { "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
3915 { "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
3916 { "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
3917 { "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
3918 { "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
3919 { "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
3920 { "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
3921 { "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
3922 { "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
3923 { "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
3924 { "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
3925 { "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
3926 { "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
3927 { "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
3928 { "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
3929 { "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
3930 { "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
3931 { "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
3932 { "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
3933 { "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
3934 { "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
3935 { "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
3936 { "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
3937 { "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
3938 { "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
3939 { "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
3940 { "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
3941 { "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
3942 { "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
3943 { "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
3944 { "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
3945 { "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
3946 { "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
3947 { "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3948 { "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
3949 { "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
3950 { "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } },
3951 { "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } },
3952 { "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } },
3953 { "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
3954 { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3955 { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3956 { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3957 { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3958 { "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3959 { "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3960 RT } },
3961 { "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3962 { "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3963 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
3964 { "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3965 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
3966 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
3967 { "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } },
3968 { "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3969 { "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3970 { "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3971 { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3972 { "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3973 { "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3974 { "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3975 { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3976 { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3977 { "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3978 { "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3979 { "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3980 { "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3981 { "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3982 { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3983 { "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3984 { "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3985 { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3986 { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3987 { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3988 { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3989 { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
3990 { "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3991 { "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3992 { "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3993 { "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3994 { "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3995 { "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3996 { "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
3997 { "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
3998 { "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
3999 { "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
4000 { "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
4001 { "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
4002 { "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
4003 { "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
4004 { "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
4005 { "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
4006 { "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
4007 { "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
4008 { "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
4009 { "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
4010 { "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
4011 { "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
4012 { "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
4013 { "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
4014 { "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
4015 { "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
4016 { "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
4017 { "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
4018 { "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
4019 { "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
4020 { "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
4021 { "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
4022 { "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
4023 { "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
4024 { "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
4025 { "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
4026 { "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
4027 { "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
4028 { "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
4029 { "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
4031 { "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
4036 { "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
4038 { "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } },
4045 { "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
4046 { "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
4047 { "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
4048 { "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
4050 { "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
4051 { "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
4052 { "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
4053 { "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
4057 { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
4059 { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
4061 { "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
4067 { "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
4068 { "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
4070 { "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
4071 { "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
4103 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
4157 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4158 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4160 { "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4161 { "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4162 { "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4163 { "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4165 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4166 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4168 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
4169 { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
4170 { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
4171 { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
4334 { "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
4340 { "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
4341 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4342 { "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
4343 { "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
4344 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4345 { "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
4347 { "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4348 { "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4349 { "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4350 { "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4352 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4353 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4355 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4356 { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4357 { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4358 { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4364 { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
4373 { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
4375 { "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } },
4377 { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } },
4378 { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4380 { "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } },
4381 { "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4399 { "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } },
4411 { "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
4413 { "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } },
4414 { "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } },
4428 { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4436 { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4478 { "mftgpr", XRC(31,735,0), XRA_MASK, POWER6, { RT, FRB } },
4494 { "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB } },
4496 { "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
4506 { "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } },
4508 { "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } },
4509 { "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } },
4511 { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4513 { "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } },
4523 { "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4525 { "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } },
4532 { "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } },
4539 { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4560 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4561 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
4576 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4577 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
4628 { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } },
4629 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
4631 { "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
4632 { "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } },
4634 { "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } },
4636 { "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
4648 { "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } },
4650 { "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
4652 { "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } },
4654 { "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
4660 { "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
4661 { "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } },
4690 { "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4691 { "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
4692 { "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4693 { "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
4694 { "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4695 { "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
4696 { "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4697 { "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
4705 { "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } },
4707 { "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
4709 { "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } },
4817 { "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4818 { "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } },
