Lines Matching defs:DEF
26 * DEF(name, oargs, iargs, cargs, flags)
30 DEF(end, 0, 0, 0, TCG_OPF_NOT_PRESENT) /* must be kept first */
31 DEF(nop, 0, 0, 0, TCG_OPF_NOT_PRESENT)
32 DEF(nop1, 0, 0, 1, TCG_OPF_NOT_PRESENT)
33 DEF(nop2, 0, 0, 2, TCG_OPF_NOT_PRESENT)
34 DEF(nop3, 0, 0, 3, TCG_OPF_NOT_PRESENT)
37 DEF(nopn, 0, 0, 1, TCG_OPF_NOT_PRESENT)
39 DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT)
40 DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)
43 DEF(call, 0, 1, 2, TCG_OPF_CALL_CLOBBER)
45 DEF(br, 0, 0, 1, TCG_OPF_BB_END)
54 DEF(mov_i32, 1, 1, 0, 0)
55 DEF(movi_i32, 1, 0, 1, 0)
56 DEF(setcond_i32, 1, 2, 1, 0)
57 DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32))
59 DEF(ld8u_i32, 1, 1, 1, 0)
60 DEF(ld8s_i32, 1, 1, 1, 0)
61 DEF(ld16u_i32, 1, 1, 1, 0)
62 DEF(ld16s_i32, 1, 1, 1, 0)
63 DEF(ld_i32, 1, 1, 1, 0)
64 DEF(st8_i32, 0, 2, 1, 0)
65 DEF(st16_i32, 0, 2, 1, 0)
66 DEF(st_i32, 0, 2, 1, 0)
68 DEF(add_i32, 1, 2, 0, 0)
69 DEF(sub_i32, 1, 2, 0, 0)
70 DEF(mul_i32, 1, 2, 0, 0)
71 DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
72 DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
73 DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
74 DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
75 DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
76 DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
77 DEF(and_i32, 1, 2, 0, 0)
78 DEF(or_i32, 1, 2, 0, 0)
79 DEF(xor_i32, 1, 2, 0, 0)
81 DEF(shl_i32, 1, 2, 0, 0)
82 DEF(shr_i32, 1, 2, 0, 0)
83 DEF(sar_i32, 1, 2, 0, 0)
84 DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
85 DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
86 DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))
88 DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END)
90 DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32))
91 DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32))
92 DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2_i32))
93 DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2_i32))
94 DEF(muluh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i32))
95 DEF(mulsh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i32))
96 DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | IMPL(TCG_TARGET_REG_BITS == 32))
97 DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32))
99 DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32))
100 DEF(ext16s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16s_i32))
101 DEF(ext8u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8u_i32))
102 DEF(ext16u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32))
103 DEF(bswap16_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap16_i32))
104 DEF(bswap32_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap32_i32))
105 DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32))
106 DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32))
107 DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32))
108 DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32))
109 DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32))
110 DEF(nand_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nand_i32))
111 DEF(nor_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32))
113 DEF(mov_i64, 1, 1, 0, IMPL64)
114 DEF(movi_i64, 1, 0, 1, IMPL64)
115 DEF(setcond_i64, 1, 2, 1, IMPL64)
116 DEF(movcond_i64, 1, 4, 1, IMPL64 | IMPL(TCG_TARGET_HAS_movcond_i64))
118 DEF(ld8u_i64, 1, 1, 1, IMPL64)
119 DEF(ld8s_i64, 1, 1, 1, IMPL64)
120 DEF(ld16u_i64, 1, 1, 1, IMPL64)
121 DEF(ld16s_i64, 1, 1, 1, IMPL64)
122 DEF(ld32u_i64, 1, 1, 1, IMPL64)
123 DEF(ld32s_i64, 1, 1, 1, IMPL64)
124 DEF(ld_i64, 1, 1, 1, IMPL64)
125 DEF(st8_i64, 0, 2, 1, IMPL64)
126 DEF(st16_i64, 0, 2, 1, IMPL64)
127 DEF(st32_i64, 0, 2, 1, IMPL64)
128 DEF(st_i64, 0, 2, 1, IMPL64)
130 DEF(add_i64, 1, 2, 0, IMPL64)
131 DEF(sub_i64, 1, 2, 0, IMPL64)
132 DEF(mul_i64, 1, 2, 0, IMPL64)
133 DEF(div_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
134 DEF(divu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
135 DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
136 DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
137 DEF(div2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
138 DEF(divu2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
139 DEF(and_i64, 1, 2, 0, IMPL64)
140 DEF(or_i64, 1, 2, 0, IMPL64)
141 DEF(xor_i64, 1, 2, 0, IMPL64)
143 DEF(shl_i64, 1, 2, 0, IMPL64)
144 DEF(shr_i64, 1, 2, 0, IMPL64)
145 DEF(sar_i64, 1, 2, 0, IMPL64)
146 DEF(rotl_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
147 DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
148 DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64))
150 DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | IMPL64)
151 DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64))
152 DEF(ext16s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16s_i64))
153 DEF(ext32s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32s_i64))
154 DEF(ext8u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8u_i64))
155 DEF(ext16u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16u_i64))
156 DEF(ext32u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32u_i64))
157 DEF(bswap16_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap16_i64))
158 DEF(bswap32_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap32_i64))
159 DEF(bswap64_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap64_i64))
160 DEF(not_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_not_i64))
161 DEF(neg_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_neg_i64))
162 DEF(andc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_andc_i64))
163 DEF(orc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_orc_i64))
164 DEF(eqv_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_eqv_i64))
165 DEF(nand_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nand_i64))
166 DEF(nor_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nor_i64))
168 DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64))
169 DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64))
170 DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2_i64))
171 DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64))
172 DEF(muluh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i64))
173 DEF(mulsh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i64))
177 DEF(debug_insn_start, 0, 0, 2, TCG_OPF_NOT_PRESENT)
179 DEF(debug_insn_start, 0, 0, 1, TCG_OPF_NOT_PRESENT)
181 DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END)
182 DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END)
189 DEF(qemu_ld_i32, 1, 1, 2, IMPL_NEW_LDST)
190 DEF(qemu_st_i32, 0, 2, 2, IMPL_NEW_LDST)
192 DEF(qemu_ld_i64, 1, 1, 2, IMPL_NEW_LDST | TCG_OPF_64BIT)
193 DEF(qemu_st_i64, 0, 2, 2, IMPL_NEW_LDST | TCG_OPF_64BIT)
195 DEF(qemu_ld_i64, 2, 1, 2, IMPL_NEW_LDST | TCG_OPF_64BIT)
196 DEF(qemu_st_i64, 0, 3, 2, IMPL_NEW_LDST | TCG_OPF_64BIT)
199 DEF(qemu_ld_i32, 1, 2, 2, IMPL_NEW_LDST)
200 DEF(qemu_st_i32, 0, 3, 2, IMPL_NEW_LDST)
201 DEF(qemu_ld_i64, 2, 2, 2, IMPL_NEW_LDST | TCG_OPF_64BIT)
202 DEF(qemu_st_i64, 0, 4, 2, IMPL_NEW_LDST | TCG_OPF_64BIT)
213 DEF(qemu_ld8u, 1, 1, 1, IMPL_OLD_LDST)
215 DEF(qemu_ld8u, 1, 2, 1, IMPL_OLD_LDST)
218 DEF(qemu_ld8s, 1, 1, 1, IMPL_OLD_LDST)
220 DEF(qemu_ld8s, 1, 2, 1, IMPL_OLD_LDST)
223 DEF(qemu_ld16u, 1, 1, 1, IMPL_OLD_LDST)
225 DEF(qemu_ld16u, 1, 2, 1, IMPL_OLD_LDST)
228 DEF(qemu_ld16s, 1, 1, 1, IMPL_OLD_LDST)
230 DEF(qemu_ld16s, 1, 2, 1, IMPL_OLD_LDST)
233 DEF(qemu_ld32, 1, 1, 1, IMPL_OLD_LDST)
235 DEF(qemu_ld32, 1, 2, 1, IMPL_OLD_LDST)
238 DEF(qemu_ld64, 2, 1, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
240 DEF(qemu_ld64, 2, 2, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
244 DEF(qemu_st8, 0, 2, 1, IMPL_OLD_LDST)
246 DEF(qemu_st8, 0, 3, 1, IMPL_OLD_LDST)
249 DEF(qemu_st16, 0, 2, 1, IMPL_OLD_LDST)
251 DEF(qemu_st16, 0, 3, 1, IMPL_OLD_LDST)
254 DEF(qemu_st32, 0, 2, 1, IMPL_OLD_LDST)
256 DEF(qemu_st32, 0, 3, 1, IMPL_OLD_LDST)
259 DEF(qemu_st64, 0, 3, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
261 DEF(qemu_st64, 0, 4, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
266 DEF(qemu_ld8u, 1, 1, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
267 DEF(qemu_ld8s, 1, 1, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
268 DEF(qemu_ld16u, 1, 1, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
269 DEF(qemu_ld16s, 1, 1, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
270 DEF(qemu_ld32, 1, 1, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
271 DEF(qemu_ld32u, 1, 1, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
272 DEF(qemu_ld32s, 1, 1, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
273 DEF(qemu_ld64, 1, 1, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
275 DEF(qemu_st8, 0, 2, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
276 DEF(qemu_st16, 0, 2, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
277 DEF(qemu_st32, 0, 2, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
278 DEF(qemu_st64, 0, 2, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
286 #undef DEF
