Lines Matching refs:xN
3820 /* STURB Wd, [Xn|SP + simm9]: 00 111000 000 simm9 00 n d
3821 LDURB Wd, [Xn|SP + simm9]: 00 111000 010 simm9 00 n d
3832 /* STRB Wd, [Xn|SP + uimm12 * 1]: 00 111 001 00 imm12 n d
3833 LDRB Wd, [Xn|SP + uimm12 * 1]: 00 111 001 01 imm12 n d
3838 UInt xN = iregNo(am->ARM64am.RI12.reg);
3839 vassert(xN <= 30);
3841 uimm12, xN, wD);
3846 /* STRB Xd, [Xn|SP, Xm]: 00 111 000 001 m 011 0 10 n d
3847 LDRB Xd, [Xn|SP, Xm]: 00 111 000 011 m 011 0 10 n d
3849 UInt xN = iregNo(am->ARM64am.RR.base);
3851 vassert(xN <= 30);
3853 xM, X011010, xN, wD);
3869 /* STURH Wd, [Xn|SP + simm9]: 01 111000 000 simm9 00 n d
3870 LDURH Wd, [Xn|SP + simm9]: 01 111000 010 simm9 00 n d
3881 /* STRH Wd, [Xn|SP + uimm12 * 2]: 01 111 001 00 imm12 n d
3882 LDRH Wd, [Xn|SP + uimm12 * 2]: 01 111 001 01 imm12 n d
3887 UInt xN = iregNo(am->ARM64am.RI12.reg);
3888 vassert(xN <= 30);
3890 uimm12, xN, wD);
3895 /* STRH Xd, [Xn|SP, Xm]: 01 111 000 001 m 011 0 10 n d
3896 LDRH Xd, [Xn|SP, Xm]: 01 111 000 011 m 011 0 10 n d
3898 UInt xN = iregNo(am->ARM64am.RR.base);
3900 vassert(xN <= 30);
3902 xM, X011010, xN, wD);
3918 /* STUR Wd, [Xn|SP + simm9]: 10 111000 000 simm9 00 n d
3919 LDUR Wd, [Xn|SP + simm9]: 10 111000 010 simm9 00 n d
3930 /* STR Wd, [Xn|SP + uimm12 * 4]: 10 111 001 00 imm12 n d
3931 LDR Wd, [Xn|SP + uimm12 * 4]: 10 111 001 01 imm12 n d
3936 UInt xN = iregNo(am->ARM64am.RI12.reg);
3937 vassert(xN <= 30);
3939 uimm12, xN, wD);
3944 /* STR Wd, [Xn|SP, Xm]: 10 111 000 001 m 011 0 10 n d
3945 LDR Wd, [Xn|SP, Xm]: 10 111 000 011 m 011 0 10 n d
3947 UInt xN = iregNo(am->ARM64am.RR.base);
3949 vassert(xN <= 30);
3951 xM, X011010, xN, wD);
3968 /* STUR Xd, [Xn|SP + simm9]: 11 111000 000 simm9 00 n d
3969 LDUR Xd, [Xn|SP + simm9]: 11 111000 010 simm9 00 n d
3973 UInt xN = iregNo(am->ARM64am.RI9.reg);
3974 vassert(xN <= 30);
3976 simm9 & 0x1FF, X00, xN, xD);
3981 /* STR Xd, [Xn|SP + uimm12 * 8]: 11 111 001 00 imm12 n d
3982 LDR Xd, [Xn|SP + uimm12 * 8]: 11 111 001 01 imm12 n d
3987 UInt xN = iregNo(am->ARM64am.RI12.reg);
3988 vassert(xN <= 30);
3990 uimm12, xN, xD);
3995 /* STR Xd, [Xn|SP, Xm]: 11 111 000 001 m 011 0 10 n d
3996 LDR Xd, [Xn|SP, Xm]: 11 111 000 011 m 011 0 10 n d
3998 UInt xN = iregNo(am->ARM64am.RR.base);
4000 vassert(xN <= 30);
4002 xM, X011010, xN, xD);
4064 /* 1 11 10001 sh imm12 Rn Rd = SUBS Xd, Xn, #imm */
4072 /* 1 11 01011 00 0 Rm 000000 Rn Rd = SUBS Xd, Xn, Xm */
4100 /* 1 01 100100 N immR immS Rn Rd = ORR <Xd|Sp>, Xn, #imm */
4101 /* 1 00 100100 N immR immS Rn Rd = AND <Xd|Sp>, Xn, #imm */
4102 /* 1 10 100100 N immR immS Rn Rd = EOR <Xd|Sp>, Xn, #imm */
4111 /* 1 01 01010 00 0 m 000000 n d = ORR Xd, Xn, Xm */
4112 /* 1 00 01010 00 0 m 000000 n d = AND Xd, Xn, Xm */
4113 /* 1 10 01010 00 0 m 000000 n d = EOR Xd, Xn, Xm */
4130 /* 1 11 100100 N immR immS Rn Rd = ANDS Xd, Xn, #imm */
4151 /* 110 1001101 (63-sh) (64-sh) nn dd LSL Xd, Xn, sh */
4152 /* 110 1001101 sh 63 nn dd LSR Xd, Xn, sh */
4153 /* 100 1001101 sh 63 nn dd ASR Xd, Xn, sh */
4173 /* 100 1101 0110 mm 001000 nn dd LSL Xd, Xn, Xm */
4174 /* 100 1101 0110 mm 001001 nn dd LSR Xd, Xn, Xm */
4175 /* 100 1101 0110 mm 001010 nn dd ASR Xd, Xn, Xm */
4198 /* 1 10 1101 0110 00000 00010 0 nn dd CLZ Xd, Xn */
4199 /* 1 10 1101 0110 00000 00010 1 nn dd CLS Xd, Xn (unimp) */
4550 /* 100 1101 0100 mm cond 00 nn dd = CSEL Xd, Xn, Xm, cond */
4630 /* 100 11011 110 mm 011111 nn dd UMULH Xd, Xn,Xm
4631 100 11011 010 mm 011111 nn dd SMULH Xd, Xn,Xm
4632 100 11011 000 mm 011111 nn dd MUL Xd, Xn,Xm
4696 /* 10 111101 01 imm12 n t LDR St, [Xn|SP, #imm12 * 4]
4697 10 111101 00 imm12 n t STR St, [Xn|SP, #imm12 * 4]
4713 /* 11 111101 01 imm12 n t LDR Dt, [Xn|SP, #imm12 * 8]
4714 11 111101 00 imm12 n t STR Dt, [Xn|SP, #imm12 * 8]
4748 100 11110 00 1 00 010 000000 n d SCVTF Sd, Xn
4749 100 11110 01 1 00 010 000000 n d SCVTF Dd, Xn
4752 100 11110 00 1 00 011 000000 n d UCVTF Sd, Xn
4753 100 11110 01 1 00 011 000000 n d UCVTF Dd, Xn
4766 case ARM64cvt_F32_I64S: /* SCVTF Sd, Xn */
4769 case ARM64cvt_F64_I64S: /* SCVTF Dd, Xn */
4778 case ARM64cvt_F32_I64U: /* UCVTF Sd, Xn */
4781 case ARM64cvt_F64_I64U: /* UCVTF Dd, Xn */
6372 0100 1110 0000 1000 0001 11 nn dd INS Vd.D[0], Xn
6386 0100 1110 0000 1000 0001 11 nn dd INS Vd.D[0], Xn
6387 0100 1110 0001 1000 0001 11 nn dd INS Vd.D[1], Xn
