Lines Matching refs:Rt
479 void Assembler::cbz(const Register& rt,
481 Emit(SF(rt) | CBZ | ImmCmpBranch(imm19) | Rt(rt));
485 void Assembler::cbz(const Register& rt,
487 cbz(rt, UpdateAndGetInstructionOffsetTo(label));
491 void Assembler::cbnz(const Register& rt,
493 Emit(SF(rt) | CBNZ | ImmCmpBranch(imm19) | Rt(rt));
497 void Assembler::cbnz(const Register& rt,
499 cbnz(rt, UpdateAndGetInstructionOffsetTo(label));
503 void Assembler::tbz(const Register& rt,
506 VIXL_ASSERT(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSize)));
507 Emit(TBZ | ImmTestBranchBit(bit_pos) | ImmTestBranch(imm14) | Rt(rt));
511 void Assembler::tbz(const Register& rt,
514 tbz(rt, bit_pos, UpdateAndGetInstructionOffsetTo(label));
518 void Assembler::tbnz(const Register& rt,
521 VIXL_ASSERT(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSize)));
522 Emit(TBNZ | ImmTestBranchBit(bit_pos) | ImmTestBranch(imm14) | Rt(rt));
526 void Assembler::tbnz(const Register& rt,
529 tbnz(rt, bit_pos, UpdateAndGetInstructionOffsetTo(label));
1024 void Assembler::ldp(const CPURegister& rt,
1027 LoadStorePair(rt, rt2, src, LoadPairOpFor(rt, rt2));
1031 void Assembler::stp(const CPURegister& rt,
1034 LoadStorePair(rt, rt2, dst, StorePairOpFor(rt, rt2));
1038 void Assembler::ldpsw(const Register& rt,
1041 VIXL_ASSERT(rt.Is64Bits());
1042 LoadStorePair(rt, rt2, src, LDPSW_x);
1046 void Assembler::LoadStorePair(const CPURegister& rt,
1050 // 'rt' and 'rt2' can only be aliased for stores.
1051 VIXL_ASSERT(((op & LoadStorePairLBit) == 0) || !rt.Is(rt2));
1052 VIXL_ASSERT(AreSameSizeAndType(rt, rt2));
1054 Instr memop = op | Rt(rt) | Rt2(rt2) | RnSP(addr.base()) |
1073 void Assembler::ldnp(const CPURegister& rt,
1076 LoadStorePairNonTemporal(rt, rt2, src,
1077 LoadPairNonTemporalOpFor(rt, rt2));
1081 void Assembler::stnp(const CPURegister& rt,
1084 LoadStorePairNonTemporal(rt, rt2, dst,
1085 StorePairNonTemporalOpFor(rt, rt2));
1089 void Assembler::LoadStorePairNonTemporal(const CPURegister& rt,
1093 VIXL_ASSERT(!rt.Is(rt2));
1094 VIXL_ASSERT(AreSameSizeAndType(rt, rt2));
1099 Emit(op | Rt(rt) | Rt2(rt2) | RnSP(addr.base()) |
1105 void Assembler::ldrb(const Register& rt, const MemOperand& src) {
1106 LoadStore(rt, src, LDRB_w);
1110 void Assembler::strb(const Register& rt, const MemOperand& dst) {
1111 LoadStore(rt, dst, STRB_w);
1115 void Assembler::ldrsb(const Register& rt, const MemOperand& src) {
1116 LoadStore(rt, src, rt.Is64Bits() ? LDRSB_x : LDRSB_w);
1120 void Assembler::ldrh(const Register& rt, const MemOperand& src) {
1121 LoadStore(rt, src, LDRH_w);
1125 void Assembler::strh(const Register& rt, const MemOperand& dst) {
1126 LoadStore(rt, dst, STRH_w);
1130 void Assembler::ldrsh(const Register& rt, const MemOperand& src) {
1131 LoadStore(rt, src, rt.Is64Bits() ? LDRSH_x : LDRSH_w);
1135 void Assembler::ldr(const CPURegister& rt, const MemOperand& src) {
1136 LoadStore(rt, src, LoadOpFor(rt));
1140 void Assembler::str(const CPURegister& rt, const MemOperand& src) {
1141 LoadStore(rt, src, StoreOpFor(rt));
1145 void Assembler::ldrsw(const Register& rt, const MemOperand& src) {
1146 VIXL_ASSERT(rt.Is64Bits());
1147 LoadStore(rt, src, LDRSW_x);
1151 void Assembler::ldr(const Register& rt, uint64_t imm) {
1152 LoadLiteral(rt, imm, rt.Is64Bits() ? LDR_x_lit : LDR_w_lit);
1185 void Assembler::mrs(const Register& rt, SystemRegister sysreg) {
1186 VIXL_ASSERT(rt.Is64Bits());
1187 Emit(MRS | ImmSystemRegister(sysreg) | Rt(rt));
1191 void Assembler::msr(SystemRegister sysreg, const Register& rt) {
1192 VIXL_ASSERT(rt.Is64Bits());
1193 Emit(MSR | Rt(rt) | ImmSystemRegister(sysreg));
1198 Emit(HINT | ImmHint(code) | Rt(xzr));
1838 void Assembler::LoadStore(const CPURegister& rt,
1841 Instr memop = op | Rt(rt) | RnSP(addr.base());
1900 void Assembler::LoadLiteral(const CPURegister& rt,
1903 VIXL_ASSERT(is_int32(imm) || is_uint32(imm) || (rt.Is64Bits()));
1906 RecordLiteral(imm, rt.SizeInBytes());
1907 Emit(op | ImmLLiteral(0) | Rt(rt));
2067 LoadStoreOp Assembler::LoadOpFor(const CPURegister& rt) {
2068 VIXL_ASSERT(rt.IsValid());
2069 if (rt.IsRegister()) {
2070 return rt.Is64Bits() ? LDR_x : LDR_w;
2072 VIXL_ASSERT(rt.IsFPRegister());
2073 return rt.Is64Bits() ? LDR_d : LDR_s;
2078 LoadStorePairOp Assembler::LoadPairOpFor(const CPURegister& rt,
2080 VIXL_ASSERT(AreSameSizeAndType(rt, rt2));
2082 if (rt.IsRegister()) {
2083 return rt.Is64Bits() ? LDP_x : LDP_w;
2085 VIXL_ASSERT(rt.IsFPRegister());
2086 return rt.Is64Bits() ? LDP_d : LDP_s;
2091 LoadStoreOp Assembler::StoreOpFor(const CPURegister& rt) {
2092 VIXL_ASSERT(rt.IsValid());
2093 if (rt.IsRegister()) {
2094 return rt.Is64Bits() ? STR_x : STR_w;
2096 VIXL_ASSERT(rt.IsFPRegister());
2097 return rt.Is64Bits() ? STR_d : STR_s;
2102 LoadStorePairOp Assembler::StorePairOpFor(const CPURegister& rt,
2104 VIXL_ASSERT(AreSameSizeAndType(rt, rt2));
2106 if (rt.IsRegister()) {
2107 return rt.Is64Bits() ? STP_x : STP_w;
2109 VIXL_ASSERT(rt.IsFPRegister());
2110 return rt.Is64Bits() ? STP_d : STP_s;
2116 const CPURegister& rt, const CPURegister& rt2) {
2117 VIXL_ASSERT(AreSameSizeAndType(rt, rt2));
2119 if (rt.IsRegister()) {
2120 return rt.Is64Bits() ? LDNP_x : LDNP_w;
2122 VIXL_ASSERT(rt.IsFPRegister());
2123 return rt.Is64Bits() ? LDNP_d : LDNP_s;
2129 const CPURegister& rt, const CPURegister& rt2) {
2130 VIXL_ASSERT(AreSameSizeAndType(rt, rt2));
2132 if (rt.IsRegister()) {
2133 return rt.Is64Bits() ? STNP_x : STNP_w;
2135 VIXL_ASSERT(rt.IsFPRegister());
2136 return rt.Is64Bits() ? STNP_d : STNP_s;
2224 Instr marker_instruction = LDR_x_lit | ImmLLiteral(pool_size) | Rt(xzr);
