Lines Matching refs:shift_amount
214 Operand::Operand(Register reg, Shift shift, unsigned shift_amount)
218 shift_amount_(shift_amount) {
219 VIXL_ASSERT(reg.Is64Bits() || (shift_amount < kWRegSize));
220 VIXL_ASSERT(reg.Is32Bits() || (shift_amount < kXRegSize));
225 Operand::Operand(Register reg, Extend extend, unsigned shift_amount)
229 shift_amount_(shift_amount) {
231 VIXL_ASSERT(shift_amount <= 4);
280 unsigned shift_amount)
282 shift_(NO_SHIFT), extend_(extend), shift_amount_(shift_amount) {
295 unsigned shift_amount)
297 shift_(shift), extend_(NO_EXTEND), shift_amount_(shift_amount) {
315 shift_amount_ = offset.shift_amount();
329 shift_amount_ = offset.shift_amount();
1627 VIXL_ASSERT(operand.IsShiftedRegister() && (operand.shift_amount() == 0));
1705 VIXL_ASSERT(operand.IsShiftedRegister() && (operand.shift_amount() == 0));
1750 unsigned shift_amount) {
1753 lsl(rd, rn, shift_amount);
1756 lsr(rd, rn, shift_amount);
1759 asr(rd, rn, shift_amount);
1762 ror(rd, rn, shift_amount);
1814 is_uint5(operand.shift_amount())));
1816 ShiftDP(operand.shift()) | ImmDPShift(operand.shift_amount()) |
1828 ExtendMode(operand.extend()) | ImmExtendShift(operand.shift_amount()) |
1860 unsigned shift_amount = addr.shift_amount();
1869 VIXL_ASSERT((shift_amount == 0) ||
1870 (shift_amount == static_cast<unsigned>(CalcLSDataSize(op))));
1872 ExtendMode(ext) | ImmShiftLS((shift_amount > 0) ? 1 : 0));
