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Lines Matching refs:reg_size

932     unsigned reg_size = rd.size();
933     VIXL_ASSERT(shift < reg_size);
934     ubfm(rd, rn, (reg_size - shift) % reg_size, reg_size - shift - 1);
1513   static inline Instr ImmS(unsigned imms, unsigned reg_size) {
1514     VIXL_ASSERT(((reg_size == kXRegSize) && is_uint6(imms)) ||
1515            ((reg_size == kWRegSize) && is_uint5(imms)));
1516     USE(reg_size);
1520   static inline Instr ImmR(unsigned immr, unsigned reg_size) {
1521     VIXL_ASSERT(((reg_size == kXRegSize) && is_uint6(immr)) ||
1522            ((reg_size == kWRegSize) && is_uint5(immr)));
1523     USE(reg_size);
1528   static inline Instr ImmSetBits(unsigned imms, unsigned reg_size) {
1529     VIXL_ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize));
1531     VIXL_ASSERT((reg_size == kXRegSize) || is_uint6(imms + 3));
1532     USE(reg_size);
1536   static inline Instr ImmRotate(unsigned immr, unsigned reg_size) {
1537     VIXL_ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize));
1538     VIXL_ASSERT(((reg_size == kXRegSize) && is_uint6(immr)) ||
1539            ((reg_size == kWRegSize) && is_uint5(immr)));
1540     USE(reg_size);
1549   static inline Instr BitN(unsigned bitn, unsigned reg_size) {
1550     VIXL_ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize));
1551     VIXL_ASSERT((reg_size == kXRegSize) || (bitn == 0));
1552     USE(reg_size);