Lines Matching refs:reg_size
128 unsigned reg_size = rd.size();
177 if (IsImmLogical(immediate, reg_size, &n, &imm_s, &imm_r)) {
291 unsigned reg_size = rd.size();
293 if (IsImmMovz(imm, reg_size) && !rd.IsSP()) {
297 } else if (IsImmMovn(imm, reg_size) && !rd.IsSP()) {
301 } else if (IsImmLogical(imm, reg_size, &n, &imm_s, &imm_r)) {
315 if (CountClearHalfWords(~imm, reg_size) >
316 CountClearHalfWords(imm, reg_size)) {
328 VIXL_ASSERT((reg_size % 16) == 0);
358 unsigned MacroAssembler::CountClearHalfWords(uint64_t imm, unsigned reg_size) {
359 VIXL_ASSERT((reg_size % 8) == 0);
361 for (unsigned i = 0; i < (reg_size / 16); i++) {
373 bool MacroAssembler::IsImmMovz(uint64_t imm, unsigned reg_size) {
374 VIXL_ASSERT((reg_size == kXRegSize) || (reg_size == kWRegSize));
375 return CountClearHalfWords(imm, reg_size) >= ((reg_size / 16) - 1);
381 bool MacroAssembler::IsImmMovn(uint64_t imm, unsigned reg_size) {
382 return IsImmMovz(~imm, reg_size);
791 // sp and reg_size is 32, registers must be pushed in blocks of four in order
811 // sp and reg_size is 32, registers must be pushed in blocks of four in order
