1 //==-- llvm/Target/TargetSubtargetInfo.h - Target Information ----*- C++ -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the subtarget options of a Target machine. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H 15 #define LLVM_TARGET_TARGETSUBTARGETINFO_H 16 17 #include "llvm/MC/MCSubtargetInfo.h" 18 #include "llvm/Support/CodeGen.h" 19 20 namespace llvm { 21 22 class MachineFunction; 23 class MachineInstr; 24 class SDep; 25 class SUnit; 26 class TargetRegisterClass; 27 class TargetSchedModel; 28 struct MachineSchedPolicy; 29 template <typename T> class SmallVectorImpl; 30 31 //===----------------------------------------------------------------------===// 32 /// 33 /// TargetSubtargetInfo - Generic base class for all target subtargets. All 34 /// Target-specific options that control code generation and printing should 35 /// be exposed through a TargetSubtargetInfo-derived class. 36 /// 37 class TargetSubtargetInfo : public MCSubtargetInfo { 38 TargetSubtargetInfo(const TargetSubtargetInfo&) LLVM_DELETED_FUNCTION; 39 void operator=(const TargetSubtargetInfo&) LLVM_DELETED_FUNCTION; 40 protected: // Can only create subclasses... 41 TargetSubtargetInfo(); 42 public: 43 // AntiDepBreakMode - Type of anti-dependence breaking that should 44 // be performed before post-RA scheduling. 45 typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode; 46 typedef SmallVectorImpl<const TargetRegisterClass*> RegClassVector; 47 48 virtual ~TargetSubtargetInfo(); 49 50 /// Resolve a SchedClass at runtime, where SchedClass identifies an 51 /// MCSchedClassDesc with the isVariant property. This may return the ID of 52 /// another variant SchedClass, but repeated invocation must quickly terminate 53 /// in a nonvariant SchedClass. 54 virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, 55 const TargetSchedModel* SchedModel) const { 56 return 0; 57 } 58 59 /// \brief Temporary API to test migration to MI scheduler. 60 bool useMachineScheduler() const; 61 62 /// \brief True if the subtarget should run MachineScheduler after aggressive 63 /// coalescing. 64 /// 65 /// This currently replaces the SelectionDAG scheduler with the "source" order 66 /// scheduler. It does not yet disable the postRA scheduler. 67 virtual bool enableMachineScheduler() const; 68 69 /// \brief True if the subtarget should run PostMachineScheduler. 70 /// 71 /// This only takes effect if the target has configured the 72 /// PostMachineScheduler pass to run, or if the global cl::opt flag, 73 /// MISchedPostRA, is set. 74 virtual bool enablePostMachineScheduler() const; 75 76 /// \brief True if the subtarget should run the atomic expansion pass. 77 virtual bool enableAtomicExpandLoadLinked() const; 78 79 /// \brief Override generic scheduling policy within a region. 80 /// 81 /// This is a convenient way for targets that don't provide any custom 82 /// scheduling heuristics (no custom MachineSchedStrategy) to make 83 /// changes to the generic scheduling policy. 84 virtual void overrideSchedPolicy(MachineSchedPolicy &Policy, 85 MachineInstr *begin, 86 MachineInstr *end, 87 unsigned NumRegionInstrs) const {} 88 89 // \brief Perform target specific adjustments to the latency of a schedule 90 // dependency. 91 virtual void adjustSchedDependency(SUnit *def, SUnit *use, 92 SDep& dep) const { } 93 94 // enablePostRAScheduler - If the target can benefit from post-regalloc 95 // scheduling and the specified optimization level meets the requirement 96 // return true to enable post-register-allocation scheduling. In 97 // CriticalPathRCs return any register classes that should only be broken 98 // if on the critical path. 99 virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, 100 AntiDepBreakMode& Mode, 101 RegClassVector& CriticalPathRCs) const; 102 103 /// \brief True if the subtarget should run the local reassignment 104 /// heuristic of the register allocator. 105 /// This heuristic may be compile time intensive, \p OptLevel provides 106 /// a finer grain to tune the register allocator. 107 virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const; 108 109 /// \brief Enable use of alias analysis during code generation (during MI 110 /// scheduling, DAGCombine, etc.). 111 virtual bool useAA() const; 112 113 /// \brief Enable the use of the early if conversion pass. 114 virtual bool enableEarlyIfConversion() const { return false; } 115 116 /// \brief Reset the features for the subtarget. 117 virtual void resetSubtargetFeatures(const MachineFunction *MF) { } 118 }; 119 120 } // End llvm namespace 121 122 #endif 123
