1 /* 2 * i386 virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef CPU_I386_H 20 #define CPU_I386_H 21 22 #include "config.h" 23 #include "qemu-common.h" 24 25 #ifdef TARGET_X86_64 26 #define TARGET_LONG_BITS 64 27 #else 28 #define TARGET_LONG_BITS 32 29 #endif 30 31 /* target supports implicit self modifying code */ 32 #define TARGET_HAS_SMC 33 /* support for self modifying code even if the modified instruction is 34 close to the modifying instruction */ 35 #define TARGET_HAS_PRECISE_SMC 36 37 #define TARGET_HAS_ICE 1 38 39 #ifdef TARGET_X86_64 40 #define ELF_MACHINE EM_X86_64 41 #else 42 #define ELF_MACHINE EM_386 43 #endif 44 45 // TODO(digit): Remove this define. 46 #define CPUOldState struct CPUX86State 47 48 #define CPUArchState struct CPUX86State 49 50 #include "exec/cpu-defs.h" 51 52 #include "fpu/softfloat.h" 53 54 #define R_EAX 0 55 #define R_ECX 1 56 #define R_EDX 2 57 #define R_EBX 3 58 #define R_ESP 4 59 #define R_EBP 5 60 #define R_ESI 6 61 #define R_EDI 7 62 63 #define R_AL 0 64 #define R_CL 1 65 #define R_DL 2 66 #define R_BL 3 67 #define R_AH 4 68 #define R_CH 5 69 #define R_DH 6 70 #define R_BH 7 71 72 #define R_ES 0 73 #define R_CS 1 74 #define R_SS 2 75 #define R_DS 3 76 #define R_FS 4 77 #define R_GS 5 78 79 /* segment descriptor fields */ 80 #define DESC_G_MASK (1 << 23) 81 #define DESC_B_SHIFT 22 82 #define DESC_B_MASK (1 << DESC_B_SHIFT) 83 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ 84 #define DESC_L_MASK (1 << DESC_L_SHIFT) 85 #define DESC_AVL_MASK (1 << 20) 86 #define DESC_P_MASK (1 << 15) 87 #define DESC_DPL_SHIFT 13 88 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) 89 #define DESC_S_MASK (1 << 12) 90 #define DESC_TYPE_SHIFT 8 91 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) 92 #define DESC_A_MASK (1 << 8) 93 94 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ 95 #define DESC_C_MASK (1 << 10) /* code: conforming */ 96 #define DESC_R_MASK (1 << 9) /* code: readable */ 97 98 #define DESC_E_MASK (1 << 10) /* data: expansion direction */ 99 #define DESC_W_MASK (1 << 9) /* data: writable */ 100 101 #define DESC_TSS_BUSY_MASK (1 << 9) 102 103 /* eflags masks */ 104 #define CC_C 0x0001 105 #define CC_P 0x0004 106 #define CC_A 0x0010 107 #define CC_Z 0x0040 108 #define CC_S 0x0080 109 #define CC_O 0x0800 110 111 #define TF_SHIFT 8 112 #define IOPL_SHIFT 12 113 #define VM_SHIFT 17 114 115 #define TF_MASK 0x00000100 116 #define IF_MASK 0x00000200 117 #define DF_MASK 0x00000400 118 #define IOPL_MASK 0x00003000 119 #define NT_MASK 0x00004000 120 #define RF_MASK 0x00010000 121 #define VM_MASK 0x00020000 122 #define AC_MASK 0x00040000 123 #define VIF_MASK 0x00080000 124 #define VIP_MASK 0x00100000 125 #define ID_MASK 0x00200000 126 127 /* hidden flags - used internally by qemu to represent additional cpu 128 states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not 129 redundant. We avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK 130 bit positions to ease oring with eflags. */ 131 /* current cpl */ 132 #define HF_CPL_SHIFT 0 133 /* true if soft mmu is being used */ 134 #define HF_SOFTMMU_SHIFT 2 135 /* true if hardware interrupts must be disabled for next instruction */ 136 #define HF_INHIBIT_IRQ_SHIFT 3 137 /* 16 or 32 segments */ 138 #define HF_CS32_SHIFT 4 139 #define HF_SS32_SHIFT 5 140 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ 141 #define HF_ADDSEG_SHIFT 6 142 /* copy of CR0.PE (protected mode) */ 143 #define HF_PE_SHIFT 7 144 #define HF_TF_SHIFT 8 /* must be same as eflags */ 145 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ 146 #define HF_EM_SHIFT 10 147 #define HF_TS_SHIFT 11 148 #define HF_IOPL_SHIFT 12 /* must be same as eflags */ 149 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ 150 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ 151 #define HF_RF_SHIFT 16 /* must be same as eflags */ 152 #define HF_VM_SHIFT 17 /* must be same as eflags */ 153 #define HF_AC_SHIFT 18 /* must be same as eflags */ 154 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ 155 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ 156 #define HF_SVMI_SHIFT 21 /* SVM intercepts are active */ 157 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ 158 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ 159 160 #define HF_CPL_MASK (3 << HF_CPL_SHIFT) 161 #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT) 162 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) 163 #define HF_CS32_MASK (1 << HF_CS32_SHIFT) 164 #define HF_SS32_MASK (1 << HF_SS32_SHIFT) 165 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) 166 #define HF_PE_MASK (1 << HF_PE_SHIFT) 167 #define HF_TF_MASK (1 << HF_TF_SHIFT) 168 #define HF_MP_MASK (1 << HF_MP_SHIFT) 169 #define HF_EM_MASK (1 << HF_EM_SHIFT) 170 #define HF_TS_MASK (1 << HF_TS_SHIFT) 171 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) 172 #define HF_LMA_MASK (1 << HF_LMA_SHIFT) 173 #define HF_CS64_MASK (1 << HF_CS64_SHIFT) 174 #define HF_RF_MASK (1 << HF_RF_SHIFT) 175 #define HF_VM_MASK (1 << HF_VM_SHIFT) 176 #define HF_AC_MASK (1 << HF_AC_SHIFT) 177 #define HF_SMM_MASK (1 << HF_SMM_SHIFT) 178 #define HF_SVME_MASK (1 << HF_SVME_SHIFT) 179 #define HF_SVMI_MASK (1 << HF_SVMI_SHIFT) 180 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) 181 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) 182 183 /* hflags2 */ 184 185 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ 186 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ 187 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ 188 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ 189 190 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) 191 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) 192 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) 193 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) 194 195 #define CR0_PE_SHIFT 0 196 #define CR0_MP_SHIFT 1 197 198 #define CR0_PE_MASK (1 << 0) 199 #define CR0_MP_MASK (1 << 1) 200 #define CR0_EM_MASK (1 << 2) 201 #define CR0_TS_MASK (1 << 3) 202 #define CR0_ET_MASK (1 << 4) 203 #define CR0_NE_MASK (1 << 5) 204 #define CR0_WP_MASK (1 << 16) 205 #define CR0_AM_MASK (1 << 18) 206 #define CR0_PG_MASK (1 << 31) 207 208 #define CR4_VME_MASK (1 << 0) 209 #define CR4_PVI_MASK (1 << 1) 210 #define CR4_TSD_MASK (1 << 2) 211 #define CR4_DE_MASK (1 << 3) 212 #define CR4_PSE_MASK (1 << 4) 213 #define CR4_PAE_MASK (1 << 5) 214 #define CR4_MCE_MASK (1 << 6) 215 #define CR4_PGE_MASK (1 << 7) 216 #define CR4_PCE_MASK (1 << 8) 217 #define CR4_OSFXSR_SHIFT 9 218 #define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT) 219 #define CR4_OSXMMEXCPT_MASK (1 << 10) 220 #define CR4_VMXE_MASK (1 << 13) 221 #define CR4_SMXE_MASK (1 << 14) 222 #define CR4_FSGSBASE_MASK (1 << 16) 223 #define CR4_PCIDE_MASK (1 << 17) 224 #define CR4_OSXSAVE_MASK (1 << 18) 225 #define CR4_SMEP_MASK (1 << 20) 226 #define CR4_SMAP_MASK (1 << 21) 227 228 #define DR6_BD (1 << 13) 229 #define DR6_BS (1 << 14) 230 #define DR6_BT (1 << 15) 231 #define DR6_FIXED_1 0xffff0ff0 232 233 #define DR7_GD (1 << 13) 234 #define DR7_TYPE_SHIFT 16 235 #define DR7_LEN_SHIFT 18 236 #define DR7_FIXED_1 0x00000400 237 #define DR7_LOCAL_BP_MASK 0x55 238 #define DR7_MAX_BP 4 239 #define DR7_TYPE_BP_INST 0x0 240 #define DR7_TYPE_DATA_WR 0x1 241 #define DR7_TYPE_IO_RW 0x2 242 #define DR7_TYPE_DATA_RW 0x3 243 244 #define PG_PRESENT_BIT 0 245 #define PG_RW_BIT 1 246 #define PG_USER_BIT 2 247 #define PG_PWT_BIT 3 248 #define PG_PCD_BIT 4 249 #define PG_ACCESSED_BIT 5 250 #define PG_DIRTY_BIT 6 251 #define PG_PSE_BIT 7 252 #define PG_GLOBAL_BIT 8 253 #define PG_NX_BIT 63 254 255 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) 256 #define PG_RW_MASK (1 << PG_RW_BIT) 257 #define PG_USER_MASK (1 << PG_USER_BIT) 258 #define PG_PWT_MASK (1 << PG_PWT_BIT) 259 #define PG_PCD_MASK (1 << PG_PCD_BIT) 260 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 261 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) 262 #define PG_PSE_MASK (1 << PG_PSE_BIT) 263 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) 264 #define PG_HI_USER_MASK 0x7ff0000000000000LL 265 #define PG_NX_MASK (1LL << PG_NX_BIT) 266 267 #define PG_ERROR_W_BIT 1 268 269 #define PG_ERROR_P_MASK 0x01 270 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) 271 #define PG_ERROR_U_MASK 0x04 272 #define PG_ERROR_RSVD_MASK 0x08 273 #define PG_ERROR_I_D_MASK 0x10 274 275 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ 276 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 277 278 #define MCE_CAP_DEF MCG_CTL_P 279 #define MCE_BANKS_DEF 10 280 281 #define MCG_STATUS_MCIP (1UL<<2) /* machine check in progress */ 282 283 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 284 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 285 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 286 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 287 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 288 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 289 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 290 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 291 #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 292 293 /* MISC register defines */ 294 #define MCM_ADDR_SEGOFF 0 /* segment offset */ 295 #define MCM_ADDR_LINEAR 1 /* linear address */ 296 #define MCM_ADDR_PHYS 2 /* physical address */ 297 #define MCM_ADDR_MEM 3 /* memory address */ 298 #define MCM_ADDR_GENERIC 7 /* generic */ 299 300 #define MSR_IA32_TSC 0x10 301 #define MSR_IA32_APICBASE 0x1b 302 #define MSR_IA32_APICBASE_BSP (1<<8) 303 #define MSR_IA32_APICBASE_ENABLE (1<<11) 304 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 305 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 306 #define MSR_TSC_ADJUST 0x0000003b 307 #define MSR_IA32_TSCDEADLINE 0x6e0 308 309 #define MSR_P6_PERFCTR0 0xc1 310 311 #define MSR_MTRRcap 0xfe 312 #define MSR_MTRRcap_VCNT 8 313 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) 314 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) 315 316 #define MSR_IA32_SYSENTER_CS 0x174 317 #define MSR_IA32_SYSENTER_ESP 0x175 318 #define MSR_IA32_SYSENTER_EIP 0x176 319 320 #define MSR_MCG_CAP 0x179 321 #define MSR_MCG_STATUS 0x17a 322 #define MSR_MCG_CTL 0x17b 323 324 #define MSR_P6_EVNTSEL0 0x186 325 326 #define MSR_IA32_PERF_STATUS 0x198 327 328 #define MSR_IA32_MISC_ENABLE 0x1a0 329 /* Indicates good rep/movs microcode on some processors: */ 330 #define MSR_IA32_MISC_ENABLE_DEFAULT 1 331 332 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) 333 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) 334 335 #define MSR_MTRRfix64K_00000 0x250 336 #define MSR_MTRRfix16K_80000 0x258 337 #define MSR_MTRRfix16K_A0000 0x259 338 #define MSR_MTRRfix4K_C0000 0x268 339 #define MSR_MTRRfix4K_C8000 0x269 340 #define MSR_MTRRfix4K_D0000 0x26a 341 #define MSR_MTRRfix4K_D8000 0x26b 342 #define MSR_MTRRfix4K_E0000 0x26c 343 #define MSR_MTRRfix4K_E8000 0x26d 344 #define MSR_MTRRfix4K_F0000 0x26e 345 #define MSR_MTRRfix4K_F8000 0x26f 346 347 #define MSR_PAT 0x277 348 349 #define MSR_MTRRdefType 0x2ff 350 351 #define MSR_CORE_PERF_FIXED_CTR0 0x309 352 #define MSR_CORE_PERF_FIXED_CTR1 0x30a 353 #define MSR_CORE_PERF_FIXED_CTR2 0x30b 354 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d 355 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e 356 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f 357 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 358 359 #define MSR_MC0_CTL 0x400 360 #define MSR_MC0_STATUS 0x401 361 #define MSR_MC0_ADDR 0x402 362 #define MSR_MC0_MISC 0x403 363 364 #define MSR_EFER 0xc0000080 365 366 #define MSR_EFER_SCE (1 << 0) 367 #define MSR_EFER_LME (1 << 8) 368 #define MSR_EFER_LMA (1 << 10) 369 #define MSR_EFER_NXE (1 << 11) 370 #define MSR_EFER_SVME (1 << 12) 371 #define MSR_EFER_FFXSR (1 << 14) 372 373 #define MSR_STAR 0xc0000081 374 #define MSR_LSTAR 0xc0000082 375 #define MSR_CSTAR 0xc0000083 376 #define MSR_FMASK 0xc0000084 377 #define MSR_FSBASE 0xc0000100 378 #define MSR_GSBASE 0xc0000101 379 #define MSR_KERNELGSBASE 0xc0000102 380 #define MSR_TSC_AUX 0xc0000103 381 382 #define MSR_VM_HSAVE_PA 0xc0010117 383 384 #define XSTATE_FP 1 385 #define XSTATE_SSE 2 386 #define XSTATE_YMM 4 387 388 /* CPUID feature words */ 389 typedef enum FeatureWord { 390 FEAT_1_EDX, /* CPUID[1].EDX */ 391 FEAT_1_ECX, /* CPUID[1].ECX */ 392 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ 393 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ 394 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ 395 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ 396 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ 397 FEAT_SVM, /* CPUID[8000_000A].EDX */ 398 FEATURE_WORDS, 399 } FeatureWord; 400 401 typedef uint32_t FeatureWordArray[FEATURE_WORDS]; 402 403 /* cpuid_features bits */ 404 #define CPUID_FP87 (1 << 0) 405 #define CPUID_VME (1 << 1) 406 #define CPUID_DE (1 << 2) 407 #define CPUID_PSE (1 << 3) 408 #define CPUID_TSC (1 << 4) 409 #define CPUID_MSR (1 << 5) 410 #define CPUID_PAE (1 << 6) 411 #define CPUID_MCE (1 << 7) 412 #define CPUID_CX8 (1 << 8) 413 #define CPUID_APIC (1 << 9) 414 #define CPUID_SEP (1 << 11) /* sysenter/sysexit */ 415 #define CPUID_MTRR (1 << 12) 416 #define CPUID_PGE (1 << 13) 417 #define CPUID_MCA (1 << 14) 418 #define CPUID_CMOV (1 << 15) 419 #define CPUID_PAT (1 << 16) 420 #define CPUID_PSE36 (1 << 17) 421 #define CPUID_PN (1 << 18) 422 #define CPUID_CLFLUSH (1 << 19) 423 #define CPUID_DTS (1 << 21) 424 #define CPUID_ACPI (1 << 22) 425 #define CPUID_MMX (1 << 23) 426 #define CPUID_FXSR (1 << 24) 427 #define CPUID_SSE (1 << 25) 428 #define CPUID_SSE2 (1 << 26) 429 #define CPUID_SS (1 << 27) 430 #define CPUID_HT (1 << 28) 431 #define CPUID_TM (1 << 29) 432 #define CPUID_IA64 (1 << 30) 433 #define CPUID_PBE (1 << 31) 434 435 #define CPUID_EXT_SSE3 (1 << 0) 436 #define CPUID_EXT_PCLMULQDQ (1 << 1) 437 #define CPUID_EXT_DTES64 (1 << 2) 438 #define CPUID_EXT_MONITOR (1 << 3) 439 #define CPUID_EXT_DSCPL (1 << 4) 440 #define CPUID_EXT_VMX (1 << 5) 441 #define CPUID_EXT_SMX (1 << 6) 442 #define CPUID_EXT_EST (1 << 7) 443 #define CPUID_EXT_TM2 (1 << 8) 444 #define CPUID_EXT_SSSE3 (1 << 9) 445 #define CPUID_EXT_CID (1 << 10) 446 #define CPUID_EXT_FMA (1 << 12) 447 #define CPUID_EXT_CX16 (1 << 13) 448 #define CPUID_EXT_XTPR (1 << 14) 449 #define CPUID_EXT_PDCM (1 << 15) 450 #define CPUID_EXT_PCID (1 << 17) 451 #define CPUID_EXT_DCA (1 << 18) 452 #define CPUID_EXT_SSE41 (1 << 19) 453 #define CPUID_EXT_SSE42 (1 << 20) 454 #define CPUID_EXT_X2APIC (1 << 21) 455 #define CPUID_EXT_MOVBE (1 << 22) 456 #define CPUID_EXT_POPCNT (1 << 23) 457 #define CPUID_EXT_TSC_DEADLINE_TIMER (1 << 24) 458 #define CPUID_EXT_AES (1 << 25) 459 #define CPUID_EXT_XSAVE (1 << 26) 460 #define CPUID_EXT_OSXSAVE (1 << 27) 461 #define CPUID_EXT_AVX (1 << 28) 462 #define CPUID_EXT_F16C (1 << 29) 463 #define CPUID_EXT_RDRAND (1 << 30) 464 #define CPUID_EXT_HYPERVISOR (1 << 31) 465 466 #define CPUID_EXT2_FPU (1 << 0) 467 #define CPUID_EXT2_VME (1 << 1) 468 #define CPUID_EXT2_DE (1 << 2) 469 #define CPUID_EXT2_PSE (1 << 3) 470 #define CPUID_EXT2_TSC (1 << 4) 471 #define CPUID_EXT2_MSR (1 << 5) 472 #define CPUID_EXT2_PAE (1 << 6) 473 #define CPUID_EXT2_MCE (1 << 7) 474 #define CPUID_EXT2_CX8 (1 << 8) 475 #define CPUID_EXT2_APIC (1 << 9) 476 #define CPUID_EXT2_SYSCALL (1 << 11) 477 #define CPUID_EXT2_MTRR (1 << 12) 478 #define CPUID_EXT2_PGE (1 << 13) 479 #define CPUID_EXT2_MCA (1 << 14) 480 #define CPUID_EXT2_CMOV (1 << 15) 481 #define CPUID_EXT2_PAT (1 << 16) 482 #define CPUID_EXT2_PSE36 (1 << 17) 483 #define CPUID_EXT2_MP (1 << 19) 484 #define CPUID_EXT2_NX (1 << 20) 485 #define CPUID_EXT2_MMXEXT (1 << 22) 486 #define CPUID_EXT2_MMX (1 << 23) 487 #define CPUID_EXT2_FXSR (1 << 24) 488 #define CPUID_EXT2_FFXSR (1 << 25) 489 #define CPUID_EXT2_PDPE1GB (1 << 26) 490 #define CPUID_EXT2_RDTSCP (1 << 27) 491 #define CPUID_EXT2_LM (1 << 29) 492 #define CPUID_EXT2_3DNOWEXT (1 << 30) 493 #define CPUID_EXT2_3DNOW (1 << 31) 494 495 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ 496 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ 497 CPUID_EXT2_DE | CPUID_EXT2_PSE | \ 498 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ 499 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ 500 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ 501 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ 502 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ 503 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ 504 CPUID_EXT2_MMX | CPUID_EXT2_FXSR) 505 506 #define CPUID_EXT3_LAHF_LM (1 << 0) 507 #define CPUID_EXT3_CMP_LEG (1 << 1) 508 #define CPUID_EXT3_SVM (1 << 2) 509 #define CPUID_EXT3_EXTAPIC (1 << 3) 510 #define CPUID_EXT3_CR8LEG (1 << 4) 511 #define CPUID_EXT3_ABM (1 << 5) 512 #define CPUID_EXT3_SSE4A (1 << 6) 513 #define CPUID_EXT3_MISALIGNSSE (1 << 7) 514 #define CPUID_EXT3_3DNOWPREFETCH (1 << 8) 515 #define CPUID_EXT3_OSVW (1 << 9) 516 #define CPUID_EXT3_IBS (1 << 10) 517 #define CPUID_EXT3_XOP (1 << 11) 518 #define CPUID_EXT3_SKINIT (1 << 12) 519 #define CPUID_EXT3_WDT (1 << 13) 520 #define CPUID_EXT3_LWP (1 << 15) 521 #define CPUID_EXT3_FMA4 (1 << 16) 522 #define CPUID_EXT3_TCE (1 << 17) 523 #define CPUID_EXT3_NODEID (1 << 19) 524 #define CPUID_EXT3_TBM (1 << 21) 525 #define CPUID_EXT3_TOPOEXT (1 << 22) 526 #define CPUID_EXT3_PERFCORE (1 << 23) 527 #define CPUID_EXT3_PERFNB (1 << 24) 528 529 #define CPUID_SVM_NPT (1 << 0) 530 #define CPUID_SVM_LBRV (1 << 1) 531 #define CPUID_SVM_SVMLOCK (1 << 2) 532 #define CPUID_SVM_NRIPSAVE (1 << 3) 533 #define CPUID_SVM_TSCSCALE (1 << 4) 534 #define CPUID_SVM_VMCBCLEAN (1 << 5) 535 #define CPUID_SVM_FLUSHASID (1 << 6) 536 #define CPUID_SVM_DECODEASSIST (1 << 7) 537 #define CPUID_SVM_PAUSEFILTER (1 << 10) 538 #define CPUID_SVM_PFTHRESHOLD (1 << 12) 539 540 #define CPUID_7_0_EBX_FSGSBASE (1 << 0) 541 #define CPUID_7_0_EBX_BMI1 (1 << 3) 542 #define CPUID_7_0_EBX_HLE (1 << 4) 543 #define CPUID_7_0_EBX_AVX2 (1 << 5) 544 #define CPUID_7_0_EBX_SMEP (1 << 7) 545 #define CPUID_7_0_EBX_BMI2 (1 << 8) 546 #define CPUID_7_0_EBX_ERMS (1 << 9) 547 #define CPUID_7_0_EBX_INVPCID (1 << 10) 548 #define CPUID_7_0_EBX_RTM (1 << 11) 549 #define CPUID_7_0_EBX_RDSEED (1 << 18) 550 #define CPUID_7_0_EBX_ADX (1 << 19) 551 #define CPUID_7_0_EBX_SMAP (1 << 20) 552 553 #define CPUID_VENDOR_SZ 12 554 555 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ 556 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ 557 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ 558 #define CPUID_VENDOR_INTEL "GenuineIntel" 559 560 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ 561 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ 562 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ 563 #define CPUID_VENDOR_AMD "AuthenticAMD" 564 565 #define CPUID_VENDOR_VIA "CentaurHauls" 566 567 #define CPUID_MWAIT_IBE (1 << 1) /* Interrupts can exit capability */ 568 #define CPUID_MWAIT_EMX (1 << 0) /* enumeration supported */ 569 570 #ifndef HYPERV_SPINLOCK_NEVER_RETRY 571 #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF 572 #endif 573 574 #define EXCP00_DIVZ 0 575 #define EXCP01_DB 1 576 #define EXCP02_NMI 2 577 #define EXCP03_INT3 3 578 #define EXCP04_INTO 4 579 #define EXCP05_BOUND 5 580 #define EXCP06_ILLOP 6 581 #define EXCP07_PREX 7 582 #define EXCP08_DBLE 8 583 #define EXCP09_XERR 9 584 #define EXCP0A_TSS 10 585 #define EXCP0B_NOSEG 11 586 #define EXCP0C_STACK 12 587 #define EXCP0D_GPF 13 588 #define EXCP0E_PAGE 14 589 #define EXCP10_COPR 16 590 #define EXCP11_ALGN 17 591 #define EXCP12_MCHK 18 592 593 #define EXCP_SYSCALL 0x100 /* only happens in user only emulation 594 for syscall instruction */ 595 596 /* i386-specific interrupt pending bits. */ 597 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 598 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 599 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 600 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 601 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 602 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_TGT_INT_1 603 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_2 604 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_3 605 606 607 typedef enum { 608 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ 609 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ 610 611 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ 612 CC_OP_MULW, 613 CC_OP_MULL, 614 CC_OP_MULQ, 615 616 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 617 CC_OP_ADDW, 618 CC_OP_ADDL, 619 CC_OP_ADDQ, 620 621 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 622 CC_OP_ADCW, 623 CC_OP_ADCL, 624 CC_OP_ADCQ, 625 626 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 627 CC_OP_SUBW, 628 CC_OP_SUBL, 629 CC_OP_SUBQ, 630 631 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 632 CC_OP_SBBW, 633 CC_OP_SBBL, 634 CC_OP_SBBQ, 635 636 CC_OP_LOGICB, /* modify all flags, CC_DST = res */ 637 CC_OP_LOGICW, 638 CC_OP_LOGICL, 639 CC_OP_LOGICQ, 640 641 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 642 CC_OP_INCW, 643 CC_OP_INCL, 644 CC_OP_INCQ, 645 646 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 647 CC_OP_DECW, 648 CC_OP_DECL, 649 CC_OP_DECQ, 650 651 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ 652 CC_OP_SHLW, 653 CC_OP_SHLL, 654 CC_OP_SHLQ, 655 656 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ 657 CC_OP_SARW, 658 CC_OP_SARL, 659 CC_OP_SARQ, 660 661 CC_OP_NB, 662 } CCOp; 663 664 typedef struct SegmentCache { 665 uint32_t selector; 666 target_ulong base; 667 uint32_t limit; 668 uint32_t flags; 669 } SegmentCache; 670 671 typedef union { 672 uint8_t _b[16]; 673 uint16_t _w[8]; 674 uint32_t _l[4]; 675 uint64_t _q[2]; 676 float32 _s[4]; 677 float64 _d[2]; 678 } XMMReg; 679 680 typedef union { 681 uint8_t _b[8]; 682 uint16_t _w[4]; 683 uint32_t _l[2]; 684 float32 _s[2]; 685 uint64_t q; 686 } MMXReg; 687 688 #ifdef WORDS_BIGENDIAN 689 #define XMM_B(n) _b[15 - (n)] 690 #define XMM_W(n) _w[7 - (n)] 691 #define XMM_L(n) _l[3 - (n)] 692 #define XMM_S(n) _s[3 - (n)] 693 #define XMM_Q(n) _q[1 - (n)] 694 #define XMM_D(n) _d[1 - (n)] 695 696 #define MMX_B(n) _b[7 - (n)] 697 #define MMX_W(n) _w[3 - (n)] 698 #define MMX_L(n) _l[1 - (n)] 699 #define MMX_S(n) _s[1 - (n)] 700 #else 701 #define XMM_B(n) _b[n] 702 #define XMM_W(n) _w[n] 703 #define XMM_L(n) _l[n] 704 #define XMM_S(n) _s[n] 705 #define XMM_Q(n) _q[n] 706 #define XMM_D(n) _d[n] 707 708 #define MMX_B(n) _b[n] 709 #define MMX_W(n) _w[n] 710 #define MMX_L(n) _l[n] 711 #define MMX_S(n) _s[n] 712 #endif 713 #define MMX_Q(n) q 714 715 typedef union { 716 floatx80 d __attribute__((aligned(16))); 717 MMXReg mmx; 718 } FPReg; 719 720 typedef struct { 721 uint64_t base; 722 uint64_t mask; 723 } MTRRVar; 724 725 #define CPU_NB_REGS64 16 726 #define CPU_NB_REGS32 8 727 728 #ifdef TARGET_X86_64 729 #define CPU_NB_REGS CPU_NB_REGS64 730 #else 731 #define CPU_NB_REGS CPU_NB_REGS32 732 #endif 733 734 #define NB_MMU_MODES 2 735 736 typedef struct CPUX86State { 737 /* standard registers */ 738 target_ulong regs[CPU_NB_REGS]; 739 target_ulong eip; 740 target_ulong eflags; /* eflags register. During CPU emulation, CC 741 flags and DF are set to zero because they are 742 stored elsewhere */ 743 744 /* emulator internal eflags handling */ 745 target_ulong cc_src; 746 target_ulong cc_dst; 747 uint32_t cc_op; 748 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ 749 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags 750 are known at translation time. */ 751 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ 752 753 /* segments */ 754 SegmentCache segs[6]; /* selector values */ 755 SegmentCache ldt; 756 SegmentCache tr; 757 SegmentCache gdt; /* only base and limit are used */ 758 SegmentCache idt; /* only base and limit are used */ 759 760 target_ulong cr[5]; /* NOTE: cr1 is unused */ 761 uint64_t a20_mask; 762 763 /* FPU state */ 764 unsigned int fpstt; /* top of stack index */ 765 unsigned int fpus; 766 unsigned int fpuc; 767 uint8_t fptags[8]; /* 0 = valid, 1 = empty */ 768 FPReg fpregs[8]; 769 770 /* emulator internal variables */ 771 float_status fp_status; 772 floatx80 ft0; 773 774 float_status mmx_status; /* for 3DNow! float ops */ 775 float_status sse_status; 776 uint32_t mxcsr; 777 XMMReg xmm_regs[CPU_NB_REGS]; 778 XMMReg xmm_t0; 779 MMXReg mmx_t0; 780 781 /* sysenter registers */ 782 uint32_t sysenter_cs; 783 target_ulong sysenter_esp; 784 target_ulong sysenter_eip; 785 uint64_t efer; 786 uint64_t star; 787 788 uint64_t vm_hsave; 789 uint64_t vm_vmcb; 790 uint64_t tsc_offset; 791 uint64_t intercept; 792 uint16_t intercept_cr_read; 793 uint16_t intercept_cr_write; 794 uint16_t intercept_dr_read; 795 uint16_t intercept_dr_write; 796 uint32_t intercept_exceptions; 797 uint8_t v_tpr; 798 799 #ifdef TARGET_X86_64 800 target_ulong lstar; 801 target_ulong cstar; 802 target_ulong fmask; 803 target_ulong kernelgsbase; 804 #endif 805 806 uint64_t tsc; 807 808 uint64_t pat; 809 810 /* exception/interrupt handling */ 811 int error_code; 812 int exception_is_int; 813 target_ulong exception_next_eip; 814 target_ulong dr[8]; /* debug registers */ 815 union { 816 CPUBreakpoint *cpu_breakpoint[4]; 817 CPUWatchpoint *cpu_watchpoint[4]; 818 }; /* break/watchpoints for dr[0..3] */ 819 uint32_t smbase; 820 int old_exception; /* exception in flight */ 821 822 CPU_COMMON 823 824 /* processor features (e.g. for CPUID insn) */ 825 uint32_t cpuid_level; 826 uint32_t cpuid_vendor1; 827 uint32_t cpuid_vendor2; 828 uint32_t cpuid_vendor3; 829 uint32_t cpuid_version; 830 uint32_t cpuid_features; 831 uint32_t cpuid_ext_features; 832 uint32_t cpuid_xlevel; 833 uint32_t cpuid_model[12]; 834 uint32_t cpuid_ext2_features; 835 uint32_t cpuid_ext3_features; 836 uint32_t cpuid_apic_id; 837 int cpuid_vendor_override; 838 839 /* MTRRs */ 840 uint64_t mtrr_fixed[11]; 841 uint64_t mtrr_deftype; 842 struct { 843 uint64_t base; 844 uint64_t mask; 845 } mtrr_var[8]; 846 847 /* For KVM */ 848 uint64_t interrupt_bitmap[256 / 64]; 849 uint32_t mp_state; 850 851 /* in order to simplify APIC support, we leave this pointer to the 852 user */ 853 struct APICState *apic_state; 854 855 uint64 mcg_cap; 856 uint64 mcg_status; 857 uint64 mcg_ctl; 858 uint64 *mce_banks; 859 } CPUX86State; 860 861 #include "cpu-qom.h" 862 863 CPUX86State *cpu_x86_init(const char *cpu_model); 864 int cpu_x86_exec(CPUX86State *s); 865 void cpu_x86_close(CPUX86State *s); 866 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf); 867 int cpu_get_pic_interrupt(CPUX86State *s); 868 /* MSDOS compatibility mode FPU exception support */ 869 void cpu_set_ferr(CPUX86State *s); 870 871 /* this function must always be used to load data in the segment 872 cache: it synchronizes the hflags with the segment cache values */ 873 static inline void cpu_x86_load_seg_cache(CPUX86State *env, 874 int seg_reg, unsigned int selector, 875 target_ulong base, 876 unsigned int limit, 877 unsigned int flags) 878 { 879 SegmentCache *sc; 880 unsigned int new_hflags; 881 882 sc = &env->segs[seg_reg]; 883 sc->selector = selector; 884 sc->base = base; 885 sc->limit = limit; 886 sc->flags = flags; 887 888 /* update the hidden flags */ 889 { 890 if (seg_reg == R_CS) { 891 #ifdef TARGET_X86_64 892 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { 893 /* long mode */ 894 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 895 env->hflags &= ~(HF_ADDSEG_MASK); 896 } else 897 #endif 898 { 899 /* legacy / compatibility case */ 900 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) 901 >> (DESC_B_SHIFT - HF_CS32_SHIFT); 902 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | 903 new_hflags; 904 } 905 } 906 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) 907 >> (DESC_B_SHIFT - HF_SS32_SHIFT); 908 if (env->hflags & HF_CS64_MASK) { 909 /* zero base assumed for DS, ES and SS in long mode */ 910 } else if (!(env->cr[0] & CR0_PE_MASK) || 911 (env->eflags & VM_MASK) || 912 !(env->hflags & HF_CS32_MASK)) { 913 /* XXX: try to avoid this test. The problem comes from the 914 fact that is real mode or vm86 mode we only modify the 915 'base' and 'selector' fields of the segment cache to go 916 faster. A solution may be to force addseg to one in 917 translate-i386.c. */ 918 new_hflags |= HF_ADDSEG_MASK; 919 } else { 920 new_hflags |= ((env->segs[R_DS].base | 921 env->segs[R_ES].base | 922 env->segs[R_SS].base) != 0) << 923 HF_ADDSEG_SHIFT; 924 } 925 env->hflags = (env->hflags & 926 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; 927 } 928 } 929 930 /* wrapper, just in case memory mappings must be changed */ 931 static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl) 932 { 933 #if HF_CPL_MASK == 3 934 s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl; 935 #else 936 #error HF_CPL_MASK is hardcoded 937 #endif 938 } 939 940 /* op_helper.c */ 941 /* used for debug or cpu save/restore */ 942 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f); 943 floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper); 944 945 /* cpu-exec.c */ 946 /* the following helpers are only usable in user mode simulation as 947 they can trigger unexpected exceptions */ 948 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); 949 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); 950 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); 951 952 /* you can call this signal handler from your SIGBUS and SIGSEGV 953 signal handlers to inform the virtual CPU of exceptions. non zero 954 is returned if the signal was handled by the virtual CPU. */ 955 int cpu_x86_signal_handler(int host_signum, void *pinfo, 956 void *puc); 957 958 /* helper.c */ 959 int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, 960 int is_write, int mmu_idx); 961 void cpu_x86_set_a20(CPUX86State *env, int a20_state); 962 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 963 uint32_t *eax, uint32_t *ebx, 964 uint32_t *ecx, uint32_t *edx); 965 966 static inline int hw_breakpoint_enabled(unsigned long dr7, int index) 967 { 968 return (dr7 >> (index * 2)) & 3; 969 } 970 971 static inline int hw_breakpoint_type(unsigned long dr7, int index) 972 { 973 return (dr7 >> (DR7_TYPE_SHIFT + (index * 2))) & 3; 974 } 975 976 static inline int hw_breakpoint_len(unsigned long dr7, int index) 977 { 978 int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 2))) & 3); 979 return (len == 2) ? 8 : len + 1; 980 } 981 982 void hw_breakpoint_insert(CPUX86State *env, int index); 983 void hw_breakpoint_remove(CPUX86State *env, int index); 984 int check_hw_breakpoints(CPUX86State *env, int force_dr6_update); 985 986 /* will be suppressed */ 987 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); 988 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); 989 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); 990 991 /* hw/apic.c */ 992 void cpu_set_apic_base(CPUX86State *env, uint64_t val); 993 uint64_t cpu_get_apic_base(CPUX86State *env); 994 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val); 995 #ifndef NO_CPU_IO_DEFS 996 uint8_t cpu_get_apic_tpr(CPUX86State *env); 997 #endif 998 999 /* hw/pc.c */ 1000 void cpu_smm_update(CPUX86State *env); 1001 uint64_t cpu_get_tsc(CPUX86State *env); 1002 1003 /* used to debug */ 1004 #define X86_DUMP_FPU 0x0001 /* dump FPU state too */ 1005 #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */ 1006 1007 #define TARGET_PAGE_BITS 12 1008 1009 #ifdef TARGET_X86_64 1010 #define TARGET_PHYS_ADDR_SPACE_BITS 52 1011 /* ??? This is really 48 bits, sign-extended, but the only thing 1012 accessible to userland with bit 48 set is the VSYSCALL, and that 1013 is handled via other mechanisms. */ 1014 #define TARGET_VIRT_ADDR_SPACE_BITS 47 1015 #else 1016 #define TARGET_PHYS_ADDR_SPACE_BITS 36 1017 #define TARGET_VIRT_ADDR_SPACE_BITS 32 1018 #endif 1019 1020 #define cpu_init cpu_x86_init 1021 #define cpu_exec cpu_x86_exec 1022 #define cpu_gen_code cpu_x86_gen_code 1023 #define cpu_signal_handler cpu_x86_signal_handler 1024 #define cpu_list x86_cpu_list 1025 1026 #define CPU_SAVE_VERSION 10 1027 1028 /* MMU modes definitions */ 1029 #define MMU_MODE0_SUFFIX _kernel 1030 #define MMU_MODE1_SUFFIX _user 1031 #define MMU_USER_IDX 1 1032 static inline int cpu_mmu_index (CPUX86State *env) 1033 { 1034 return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0; 1035 } 1036 1037 #undef EAX 1038 #define EAX (env->regs[R_EAX]) 1039 #undef ECX 1040 #define ECX (env->regs[R_ECX]) 1041 #undef EDX 1042 #define EDX (env->regs[R_EDX]) 1043 #undef EBX 1044 #define EBX (env->regs[R_EBX]) 1045 #undef ESP 1046 #define ESP (env->regs[R_ESP]) 1047 #undef EBP 1048 #define EBP (env->regs[R_EBP]) 1049 #undef ESI 1050 #define ESI (env->regs[R_ESI]) 1051 #undef EDI 1052 #define EDI (env->regs[R_EDI]) 1053 #undef EIP 1054 #define EIP (env->eip) 1055 #define DF (env->df) 1056 1057 #define CC_SRC (env->cc_src) 1058 #define CC_DST (env->cc_dst) 1059 #define CC_OP (env->cc_op) 1060 1061 /* n must be a constant to be efficient */ 1062 static inline target_long lshift(target_long x, int n) 1063 { 1064 if (n >= 0) 1065 return x << n; 1066 else 1067 return x >> (-n); 1068 } 1069 1070 /* float macros */ 1071 #define FT0 (env->ft0) 1072 #define ST0 (env->fpregs[env->fpstt].d) 1073 #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) 1074 #define ST1 ST(1) 1075 1076 /* translate.c */ 1077 void optimize_flags_init(void); 1078 1079 typedef struct CCTable { 1080 int (*compute_all)(void); /* return all the flags */ 1081 int (*compute_c)(void); /* return the C flag */ 1082 } CCTable; 1083 1084 /* XXX not defined yet. Should be fixed */ 1085 static inline int is_cpu_user(CPUX86State *env) 1086 { 1087 return 0; 1088 } 1089 1090 #if defined(CONFIG_USER_ONLY) 1091 static inline void cpu_clone_regs(CPUX86State *env, target_ulong newsp) 1092 { 1093 if (newsp) 1094 env->regs[R_ESP] = newsp; 1095 env->regs[R_EAX] = 0; 1096 } 1097 #endif 1098 1099 #include "exec/cpu-all.h" 1100 #include "svm.h" 1101 1102 static inline bool cpu_has_work(CPUState *cpu) 1103 { 1104 int work; 1105 CPUX86State *env = cpu->env_ptr; 1106 1107 work = (cpu->interrupt_request & CPU_INTERRUPT_HARD) && 1108 (env->eflags & IF_MASK); 1109 work |= cpu->interrupt_request & CPU_INTERRUPT_NMI; 1110 work |= cpu->interrupt_request & CPU_INTERRUPT_INIT; 1111 work |= cpu->interrupt_request & CPU_INTERRUPT_SIPI; 1112 1113 return work; 1114 } 1115 1116 #include "exec/exec-all.h" 1117 1118 static inline void cpu_pc_from_tb(CPUX86State *env, TranslationBlock *tb) 1119 { 1120 env->eip = tb->pc - tb->cs_base; 1121 } 1122 1123 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, 1124 target_ulong *cs_base, int *flags) 1125 { 1126 *cs_base = env->segs[R_CS].base; 1127 *pc = *cs_base + env->eip; 1128 *flags = env->hflags | 1129 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK)); 1130 } 1131 1132 void apic_init_reset(CPUX86State *env); 1133 void apic_sipi(CPUX86State *env); 1134 void do_cpu_init(CPUX86State *env); 1135 void do_cpu_sipi(CPUX86State *env); 1136 1137 /* excp_helper.c */ 1138 void do_interrupt(CPUArchState *env); 1139 void do_interrupt_x86_hardirq(CPUArchState *env, int intno, int is_hw); 1140 //void QEMU_NORETURN raise_exception_err(int exception_index, int error_code); 1141 void QEMU_NORETURN raise_exception(CPUArchState *env, int exception_index); 1142 void QEMU_NORETURN raise_exception_err(CPUX86State *env, 1143 int exception_index, 1144 int error_code); 1145 1146 void QEMU_NORETURN raise_interrupt(CPUX86State *env, 1147 int intno, int is_int, int error_code, 1148 int next_eip_addend); 1149 1150 void do_smm_enter(CPUArchState *env1); 1151 1152 void svm_check_intercept(CPUArchState *env1, uint32_t type); 1153 1154 /* cc_helper.c */ 1155 const uint8_t parity_table[256]; 1156 uint32_t cpu_cc_compute_all(CPUArchState *env1, int op); 1157 1158 static inline uint32_t cpu_compute_eflags(CPUX86State *env) 1159 { 1160 return env->eflags | cpu_cc_compute_all(env, CC_OP) | (DF & DF_MASK); 1161 } 1162 1163 /* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */ 1164 static inline void cpu_load_eflags(CPUX86State *env, 1165 int eflags, int update_mask) 1166 { 1167 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); 1168 DF = 1 - (2 * ((eflags >> 10) & 1)); 1169 env->eflags = (env->eflags & ~update_mask) | 1170 (eflags & update_mask) | 0x2; 1171 } 1172 1173 /* load efer and update the corresponding hflags. XXX: do consistency 1174 checks with cpuid bits ? */ 1175 static inline void cpu_load_efer(CPUX86State *env, uint64_t val) 1176 { 1177 env->efer = val; 1178 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); 1179 if (env->efer & MSR_EFER_LMA) 1180 env->hflags |= HF_LMA_MASK; 1181 if (env->efer & MSR_EFER_SVME) 1182 env->hflags |= HF_SVME_MASK; 1183 } 1184 1185 1186 #endif /* CPU_I386_H */ 1187
