HomeSort by relevance Sort by last modified time
    Searched defs:Dst (Results 1 - 25 of 47) sorted by null

1 2

  /external/llvm/lib/Target/R600/MCTargetDesc/
AMDGPUAsmBackend.cpp 76 uint16_t *Dst = (uint16_t*)(Data + Fixup.getOffset());
78 *Dst = (Value - 4) / 4;
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/
radeon_variable.h 46 struct rc_dst_register Dst;
  /external/llvm/include/llvm/Target/
CostTable.h 51 TypeTy Dst;
60 unsigned len, int ISD, CompareTy Dst,
63 if (ISD == Tbl[i].ISD && Src == Tbl[i].Src && Dst == Tbl[i].Dst)
74 int ISD, CompareTy Dst, CompareTy Src) {
75 return ConvertCostTableLookup(Tbl, N, ISD, Dst, Src);
  /external/mesa3d/src/gallium/drivers/r300/compiler/
radeon_variable.h 46 struct rc_dst_register Dst;
  /external/llvm/lib/Support/
ConvertUTFWrapper.cpp 114 UTF8 *Dst = reinterpret_cast<UTF8 *>(&Out[0]);
115 UTF8 *DstEnd = Dst + Out.size();
118 ConvertUTF16toUTF8(&Src, SrcEnd, &Dst, DstEnd, strictConversion);
126 Out.resize(reinterpret_cast<char *>(Dst) - &Out[0]);
  /external/llvm/lib/IR/
GCOV.cpp 156 uint32_t Dst;
157 if (!Buff.readInt(Dst)) return false;
158 Edges.push_back(make_unique<GCOVEdge>(*Blocks[BlockNo], *Blocks[Dst]));
161 Blocks[Dst]->addSrcEdge(Edge);
335 if (!DstEdges[DstEdgeNo]->Dst.getNumDstEdges())
336 DstEdges[DstEdgeNo]->Dst.Counter += N;
371 dbgs() << Edge->Dst.Number << " (" << Edge->Count << "), ";
  /external/llvm/lib/Target/ARM/InstPrinter/
ARMInstPrinter.cpp 112 const MCOperand &Dst = MI->getOperand(0);
122 printRegName(O, Dst.getReg());
135 const MCOperand &Dst = MI->getOperand(0);
144 printRegName(O, Dst.getReg());
    [all...]
  /external/llvm/lib/Target/AArch64/
AArch64AdvSIMDScalarPass.cpp 229 unsigned Dst = MI->getOperand(0).getReg();
232 Use = MRI->use_instr_nodbg_begin(Dst),
265 unsigned Dst, unsigned Src, bool IsKill) {
268 Dst)
333 unsigned Dst = MRI->createVirtualRegister(&AArch64::FPR64RegClass);
338 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(NewOpc), Dst)
345 insertCopy(TII, MI, MI->getOperand(0).getReg(), Dst, true);
  /external/llvm/lib/Target/Hexagon/
HexagonPeephole.cpp 104 void ChangeOpInto(MachineOperand &Dst, MachineOperand &Src);
140 MachineOperand &Dst = MI->getOperand(0);
142 unsigned DstReg = Dst.getReg();
159 MachineOperand &Dst = MI->getOperand(0);
164 unsigned DstReg = Dst.getReg();
176 MachineOperand &Dst = MI->getOperand(0);
181 unsigned DstReg = Dst.getReg();
191 MachineOperand &Dst = MI->getOperand(0);
193 unsigned DstReg = Dst.getReg();
209 MachineOperand &Dst = MI->getOperand(0)
    [all...]
  /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/tgsi/
tgsi_parse.h 99 struct tgsi_full_dst_register Dst[TGSI_FULL_MAX_DST_REGISTERS];
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/tests/
rc_test_helpers.c 227 fprintf(stderr, "Failed to execute regex for dst register.\n");
245 fprintf(stderr, "Unknown dst register file type.\n");
254 fprintf(stderr, "Could not convert dst register index\n");
287 DBG("Dst Reg File=%u Index=%d Writemask=%d\n",
299 struct match_info Dst;
353 tokens.Dst.String = inst_str + matches[3].rm_so;
354 tokens.Dst.Length = match_length(matches, 3);
357 dst_str = malloc(sizeof(char) * (tokens.Dst.Length + 1));
358 strncpy(dst_str, tokens.Dst.String, tokens.Dst.Length)
    [all...]
  /external/clang/lib/StaticAnalyzer/Core/
CoreEngine.cpp 274 ExplodedNodeSet &Dst) {
278 Dst.Add(*I);
457 ExplodedNodeSet Dst;
458 SubEng.processBranch(Cond, Term, Ctx, Pred, Dst,
461 enqueue(Dst);
469 ExplodedNodeSet Dst;
470 SubEng.processStaticInitializer(DS, Ctx, Pred, Dst,
473 enqueue(Dst);
ExprEngineCXX.cpp 27 ExplodedNodeSet &Dst) {
28 StmtNodeBuilder Bldr(Pred, Dst, *currBldrCtx);
58 ExplodedNodeSet Dst;
71 evalBind(Dst, CallExpr, Pred, ThisVal, V, true);
74 for (ExplodedNodeSet::iterator I = Dst.begin(), E = Dst.end();
304 ExplodedNodeSet &Dst) {
340 getCheckerManager().runCheckersForPostCall(Dst, DstInvalidated,
346 ExplodedNodeSet &Dst) {
365 getCheckerManager().runCheckersForPostCall(Dst, DstInvalidated
    [all...]
ExprEngineCallAndReturn.cpp 161 ExplodedNodeSet &Dst) {
167 Dst.Add(Pred);
178 removeDead(Pred, Dst, dyn_cast<ReturnStmt>(LastSt), LCtx,
322 // CEENode -> Dst -> WorkList
335 ExplodedNodeSet Dst;
337 getCheckerManager().runCheckersForPostObjCMessage(Dst, DstPostCall, *Msg,
341 getCheckerManager().runCheckersForPostStmt(Dst, DstPostCall, CE,
344 Dst.insert(DstPostCall);
348 for (ExplodedNodeSet::iterator PSI = Dst.begin(), PSE = Dst.end()
    [all...]
  /external/llvm/lib/Target/R600/
R600Packetizer.cpp 93 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst);
97 unsigned Dst = BI->getOperand(DstIdx).getReg();
99 Result[Dst] = AMDGPU::PS;
104 Result[Dst] = AMDGPU::PV_X;
107 if (Dst == AMDGPU::OQAP) {
111 switch (TRI.getHWRegChan(Dst)) {
127 Result[Dst] = PVReg;
241 // Is the dst reg sequence legal ?
SILowerControlFlow.cpp 200 unsigned Dst = MI.getOperand(0).getReg();
204 TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst)
209 .addReg(Dst);
220 unsigned Dst = MI.getOperand(0).getReg();
223 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
234 unsigned Dst = MI.getOperand(0).getReg();
238 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
249 unsigned Dst = MI.getOperand(0).getReg();
253 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
404 unsigned Dst = MI.getOperand(0).getReg()
    [all...]
  /external/llvm/lib/Target/Sparc/
SparcInstrInfo.cpp 338 unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]);
340 assert(Dst && Src && "Bad sub-register");
342 MovMI = BuildMI(MBB, I, DL, get(movOpc), Dst).addReg(Src);
  /external/llvm/lib/Target/X86/
X86FixupLEAs.cpp 304 const MachineOperand &Dst = MI->getOperand(0);
310 .addOperand(Dst)
320 .addOperand(Dst)
  /external/mesa3d/src/gallium/auxiliary/tgsi/
tgsi_parse.h 99 struct tgsi_full_dst_register Dst[TGSI_FULL_MAX_DST_REGISTERS];
  /external/mesa3d/src/gallium/drivers/r300/compiler/tests/
rc_test_helpers.c 227 fprintf(stderr, "Failed to execute regex for dst register.\n");
245 fprintf(stderr, "Unknown dst register file type.\n");
254 fprintf(stderr, "Could not convert dst register index\n");
287 DBG("Dst Reg File=%u Index=%d Writemask=%d\n",
299 struct match_info Dst;
353 tokens.Dst.String = inst_str + matches[3].rm_so;
354 tokens.Dst.Length = match_length(matches, 3);
357 dst_str = malloc(sizeof(char) * (tokens.Dst.Length + 1));
358 strncpy(dst_str, tokens.Dst.String, tokens.Dst.Length)
    [all...]
  /external/llvm/lib/Target/Mips/
MipsSEFrameLowering.cpp 136 unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
139 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst)
180 unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
181 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
182 unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
242 unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
243 unsigned VRegSize = RegInfo.getMinimalPhysRegClass(Dst)->getSize() / 2;
248 unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
249 unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
MipsSEInstrInfo.cpp 493 const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
494 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/i915/
i915_fpc.h 303 struct i915_full_dst_register Dst[1];
  /external/llvm/include/llvm/Analysis/
DependenceAnalysis.h 75 Dst(Destination),
108 Instruction *getDst() const { return Dst; }
204 Instruction *Src, *Dst;
221 Instruction *Dst,
284 /// depends - Tests for a dependence between the Src and Dst instructions.
288 /// if it appears that control flow can reach from Src to Dst
291 Instruction *Dst,
347 const SCEV *Dst;
459 /// establishNestingLevels - Examines the loop nesting of the Src and Dst
476 /// ... - loops containing Src but not Dst
    [all...]
  /external/llvm/include/llvm/Support/
GCOV.h 253 GCOVEdge(GCOVBlock &S, GCOVBlock &D) : Src(S), Dst(D), Count(0) {}
256 GCOVBlock &Dst;
294 EdgeWeight(GCOVBlock *D): Dst(D), Count(0) {}
296 GCOVBlock *Dst;
302 return E1->Dst.Number < E2->Dst.Number;
318 assert(&Edge->Dst == this); // up to caller to ensure edge is valid
324 if (DstEdges.size() && DstEdges.back()->Dst.Number > Edge->Dst.Number)

Completed in 1845 milliseconds

1 2