1 /* 2 * Copyright (c) 2011 Intel Corporation. All Rights Reserved. 3 * Copyright (c) Imagination Technologies Limited, UK 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 27 /****************************************************************************** 28 29 @File msvdx_mtx_reg_io2.h 30 31 @Title MSVDX MMU defines 32 33 @Platform </b>\n 34 35 @Description </b>\n This file contains the MSVDX_MTX_REG_IO2_H Defintions. 36 37 ******************************************************************************/ 38 #if !defined (__MSVDX_MTX_REG_IO2_H__) 39 #define __MSVDX_MTX_REG_IO2_H__ 40 41 #ifdef __cplusplus 42 extern "C" { 43 #endif 44 45 46 #define MTX_CORE_CR_MTX_ENABLE_OFFSET (0x0000) 47 48 // MTX_CORE CR_MTX_ENABLE MTX_MAJ_REV 49 #define MTX_CORE_CR_MTX_ENABLE_MTX_MAJ_REV_MASK (0xFF000000) 50 #define MTX_CORE_CR_MTX_ENABLE_MTX_MAJ_REV_LSBMASK (0x000000FF) 51 #define MTX_CORE_CR_MTX_ENABLE_MTX_MAJ_REV_SHIFT (24) 52 53 // MTX_CORE CR_MTX_ENABLE MTX_MIN_REV 54 #define MTX_CORE_CR_MTX_ENABLE_MTX_MIN_REV_MASK (0x00FF0000) 55 #define MTX_CORE_CR_MTX_ENABLE_MTX_MIN_REV_LSBMASK (0x000000FF) 56 #define MTX_CORE_CR_MTX_ENABLE_MTX_MIN_REV_SHIFT (16) 57 58 // MTX_CORE CR_MTX_ENABLE MTX_TCAPS 59 #define MTX_CORE_CR_MTX_ENABLE_MTX_TCAPS_MASK (0x0000F000) 60 #define MTX_CORE_CR_MTX_ENABLE_MTX_TCAPS_LSBMASK (0x0000000F) 61 #define MTX_CORE_CR_MTX_ENABLE_MTX_TCAPS_SHIFT (12) 62 63 // MTX_CORE CR_MTX_ENABLE MTX_ARCH 64 #define MTX_CORE_CR_MTX_ENABLE_MTX_ARCH_MASK (0x00000800) 65 #define MTX_CORE_CR_MTX_ENABLE_MTX_ARCH_LSBMASK (0x00000001) 66 #define MTX_CORE_CR_MTX_ENABLE_MTX_ARCH_SHIFT (11) 67 68 // MTX_CORE CR_MTX_ENABLE MTX_STEP_REC 69 #define MTX_CORE_CR_MTX_ENABLE_MTX_STEP_REC_MASK (0x000000F0) 70 #define MTX_CORE_CR_MTX_ENABLE_MTX_STEP_REC_LSBMASK (0x0000000F) 71 #define MTX_CORE_CR_MTX_ENABLE_MTX_STEP_REC_SHIFT (4) 72 73 // MTX_CORE CR_MTX_ENABLE MTX_TSTOPPED 74 #define MTX_CORE_CR_MTX_ENABLE_MTX_TSTOPPED_MASK (0x00000004) 75 #define MTX_CORE_CR_MTX_ENABLE_MTX_TSTOPPED_LSBMASK (0x00000001) 76 #define MTX_CORE_CR_MTX_ENABLE_MTX_TSTOPPED_SHIFT (2) 77 78 // MTX_CORE CR_MTX_ENABLE MTX_TOFF 79 #define MTX_CORE_CR_MTX_ENABLE_MTX_TOFF_MASK (0x00000002) 80 #define MTX_CORE_CR_MTX_ENABLE_MTX_TOFF_LSBMASK (0x00000001) 81 #define MTX_CORE_CR_MTX_ENABLE_MTX_TOFF_SHIFT (1) 82 83 // MTX_CORE CR_MTX_ENABLE MTX_ENABLE 84 #define MTX_CORE_CR_MTX_ENABLE_MTX_ENABLE_MASK (0x00000001) 85 #define MTX_CORE_CR_MTX_ENABLE_MTX_ENABLE_LSBMASK (0x00000001) 86 #define MTX_CORE_CR_MTX_ENABLE_MTX_ENABLE_SHIFT (0) 87 88 #define MTX_CORE_CR_MTX_STATUS_OFFSET (0x0008) 89 90 // MTX_CORE CR_MTX_STATUS MTX_HREASON 91 #define MTX_CORE_CR_MTX_STATUS_MTX_HREASON_MASK (0x000C0000) 92 #define MTX_CORE_CR_MTX_STATUS_MTX_HREASON_LSBMASK (0x00000003) 93 #define MTX_CORE_CR_MTX_STATUS_MTX_HREASON_SHIFT (18) 94 95 // MTX_CORE CR_MTX_STATUS MTX_LSM_STEP 96 #define MTX_CORE_CR_MTX_STATUS_MTX_LSM_STEP_MASK (0x00000700) 97 #define MTX_CORE_CR_MTX_STATUS_MTX_LSM_STEP_LSBMASK (0x00000007) 98 #define MTX_CORE_CR_MTX_STATUS_MTX_LSM_STEP_SHIFT (8) 99 100 // MTX_CORE CR_MTX_STATUS MTX_CF_Z 101 #define MTX_CORE_CR_MTX_STATUS_MTX_CF_Z_MASK (0x00000008) 102 #define MTX_CORE_CR_MTX_STATUS_MTX_CF_Z_LSBMASK (0x00000001) 103 #define MTX_CORE_CR_MTX_STATUS_MTX_CF_Z_SHIFT (3) 104 105 // MTX_CORE CR_MTX_STATUS MTX_CF_N 106 #define MTX_CORE_CR_MTX_STATUS_MTX_CF_N_MASK (0x00000004) 107 #define MTX_CORE_CR_MTX_STATUS_MTX_CF_N_LSBMASK (0x00000001) 108 #define MTX_CORE_CR_MTX_STATUS_MTX_CF_N_SHIFT (2) 109 110 // MTX_CORE CR_MTX_STATUS MTX_CR_O 111 #define MTX_CORE_CR_MTX_STATUS_MTX_CR_O_MASK (0x00000002) 112 #define MTX_CORE_CR_MTX_STATUS_MTX_CR_O_LSBMASK (0x00000001) 113 #define MTX_CORE_CR_MTX_STATUS_MTX_CR_O_SHIFT (1) 114 115 // MTX_CORE CR_MTX_STATUS MTX_CF_C 116 #define MTX_CORE_CR_MTX_STATUS_MTX_CF_C_MASK (0x00000001) 117 #define MTX_CORE_CR_MTX_STATUS_MTX_CF_C_LSBMASK (0x00000001) 118 #define MTX_CORE_CR_MTX_STATUS_MTX_CF_C_SHIFT (0) 119 120 #define MTX_CORE_CR_MTX_KICK_OFFSET (0x0080) 121 122 // MTX_CORE CR_MTX_KICK MTX_KICK 123 #define MTX_CORE_CR_MTX_KICK_MTX_KICK_MASK (0x0000FFFF) 124 #define MTX_CORE_CR_MTX_KICK_MTX_KICK_LSBMASK (0x0000FFFF) 125 #define MTX_CORE_CR_MTX_KICK_MTX_KICK_SHIFT (0) 126 127 #define MTX_CORE_CR_MTX_KICKI_OFFSET (0x0088) 128 129 // MTX_CORE CR_MTX_KICKI MTX_KICKI 130 #define MTX_CORE_CR_MTX_KICKI_MTX_KICKI_MASK (0x0000FFFF) 131 #define MTX_CORE_CR_MTX_KICKI_MTX_KICKI_LSBMASK (0x0000FFFF) 132 #define MTX_CORE_CR_MTX_KICKI_MTX_KICKI_SHIFT (0) 133 134 #define MTX_CORE_CR_MTX_FAULT0_OFFSET (0x0090) 135 136 // MTX_CORE CR_MTX_FAULT0 REQ_LD_REG 137 #define MTX_CORE_CR_MTX_FAULT0_REQ_LD_REG_MASK (0xF8000000) 138 #define MTX_CORE_CR_MTX_FAULT0_REQ_LD_REG_LSBMASK (0x0000001F) 139 #define MTX_CORE_CR_MTX_FAULT0_REQ_LD_REG_SHIFT (27) 140 141 // MTX_CORE CR_MTX_FAULT0 REQ_LD_DEST 142 #define MTX_CORE_CR_MTX_FAULT0_REQ_LD_DEST_MASK (0x00FF0000) 143 #define MTX_CORE_CR_MTX_FAULT0_REQ_LD_DEST_LSBMASK (0x000000FF) 144 #define MTX_CORE_CR_MTX_FAULT0_REQ_LD_DEST_SHIFT (16) 145 146 // MTX_CORE CR_MTX_FAULT0 REQ_STATE 147 #define MTX_CORE_CR_MTX_FAULT0_REQ_STATE_MASK (0x00000C00) 148 #define MTX_CORE_CR_MTX_FAULT0_REQ_STATE_LSBMASK (0x00000003) 149 #define MTX_CORE_CR_MTX_FAULT0_REQ_STATE_SHIFT (10) 150 151 // MTX_CORE CR_MTX_FAULT0 REQ_RN_W 152 #define MTX_CORE_CR_MTX_FAULT0_REQ_RN_W_MASK (0x00000100) 153 #define MTX_CORE_CR_MTX_FAULT0_REQ_RN_W_LSBMASK (0x00000001) 154 #define MTX_CORE_CR_MTX_FAULT0_REQ_RN_W_SHIFT (8) 155 156 // MTX_CORE CR_MTX_FAULT0 REQ_SB 157 #define MTX_CORE_CR_MTX_FAULT0_REQ_SB_MASK (0x000000FF) 158 #define MTX_CORE_CR_MTX_FAULT0_REQ_SB_LSBMASK (0x000000FF) 159 #define MTX_CORE_CR_MTX_FAULT0_REQ_SB_SHIFT (0) 160 161 #define MTX_CORE_CR_MTX_REGISTER_READ_WRITE_DATA_OFFSET (0x00F8) 162 163 #define MTX_CORE_CR_MTX_REGISTER_READ_WRITE_REQUEST_OFFSET (0x00FC) 164 165 // MTX_CORE CR_MTX_REGISTER_READ_WRITE_REQUEST MTX_DREADY 166 #define MTX_CORE_CR_MTX_REGISTER_READ_WRITE_REQUEST_MTX_DREADY_MASK (0x80000000) 167 #define MTX_CORE_CR_MTX_REGISTER_READ_WRITE_REQUEST_MTX_DREADY_LSBMASK (0x00000001) 168 #define MTX_CORE_CR_MTX_REGISTER_READ_WRITE_REQUEST_MTX_DREADY_SHIFT (31) 169 170 // MTX_CORE CR_MTX_REGISTER_READ_WRITE_REQUEST MTX_RNW 171 #define MTX_CORE_CR_MTX_REGISTER_READ_WRITE_REQUEST_MTX_RNW_MASK (0x00010000) 172 #define MTX_CORE_CR_MTX_REGISTER_READ_WRITE_REQUEST_MTX_RNW_LSBMASK (0x00000001) 173 #define MTX_CORE_CR_MTX_REGISTER_READ_WRITE_REQUEST_MTX_RNW_SHIFT (16) 174 175 // MTX_CORE CR_MTX_REGISTER_READ_WRITE_REQUEST MTX_RSPECIFIER 176 #define MTX_CORE_CR_MTX_REGISTER_READ_WRITE_REQUEST_MTX_RSPECIFIER_MASK (0x00000070) 177 #define MTX_CORE_CR_MTX_REGISTER_READ_WRITE_REQUEST_MTX_RSPECIFIER_LSBMASK (0x00000007) 178 #define MTX_CORE_CR_MTX_REGISTER_READ_WRITE_REQUEST_MTX_RSPECIFIER_SHIFT (4) 179 180 // MTX_CORE CR_MTX_REGISTER_READ_WRITE_REQUEST MTX_USPECIFIER 181 #define MTX_CORE_CR_MTX_REGISTER_READ_WRITE_REQUEST_MTX_USPECIFIER_MASK (0x0000000F) 182 #define MTX_CORE_CR_MTX_REGISTER_READ_WRITE_REQUEST_MTX_USPECIFIER_LSBMASK (0x0000000F) 183 #define MTX_CORE_CR_MTX_REGISTER_READ_WRITE_REQUEST_MTX_USPECIFIER_SHIFT (0) 184 185 #define MTX_CORE_CR_MTX_RAM_ACCESS_DATA_EXCHANGE_OFFSET (0x0100) 186 187 #define MTX_CORE_CR_MTX_RAM_ACCESS_DATA_TRANSFER_OFFSET (0x0104) 188 189 #define MTX_CORE_CR_MTX_RAM_ACCESS_CONTROL_OFFSET (0x0108) 190 191 // MTX_CORE CR_MTX_RAM_ACCESS_CONTROL MTX_MCMID 192 #define MTX_CORE_CR_MTX_RAM_ACCESS_CONTROL_MTX_MCMID_MASK (0x0FF00000) 193 #define MTX_CORE_CR_MTX_RAM_ACCESS_CONTROL_MTX_MCMID_LSBMASK (0x000000FF) 194 #define MTX_CORE_CR_MTX_RAM_ACCESS_CONTROL_MTX_MCMID_SHIFT (20) 195 196 // MTX_CORE CR_MTX_RAM_ACCESS_CONTROL MTX_MCM_ADDR 197 #define MTX_CORE_CR_MTX_RAM_ACCESS_CONTROL_MTX_MCM_ADDR_MASK (0x000FFFFC) 198 #define MTX_CORE_CR_MTX_RAM_ACCESS_CONTROL_MTX_MCM_ADDR_LSBMASK (0x0003FFFF) 199 #define MTX_CORE_CR_MTX_RAM_ACCESS_CONTROL_MTX_MCM_ADDR_SHIFT (2) 200 201 // MTX_CORE CR_MTX_RAM_ACCESS_CONTROL MTX_MCMAI 202 #define MTX_CORE_CR_MTX_RAM_ACCESS_CONTROL_MTX_MCMAI_MASK (0x00000002) 203 #define MTX_CORE_CR_MTX_RAM_ACCESS_CONTROL_MTX_MCMAI_LSBMASK (0x00000001) 204 #define MTX_CORE_CR_MTX_RAM_ACCESS_CONTROL_MTX_MCMAI_SHIFT (1) 205 206 // MTX_CORE CR_MTX_RAM_ACCESS_CONTROL MTX_MCMR 207 #define MTX_CORE_CR_MTX_RAM_ACCESS_CONTROL_MTX_MCMR_MASK (0x00000001) 208 #define MTX_CORE_CR_MTX_RAM_ACCESS_CONTROL_MTX_MCMR_LSBMASK (0x00000001) 209 #define MTX_CORE_CR_MTX_RAM_ACCESS_CONTROL_MTX_MCMR_SHIFT (0) 210 211 #define MTX_CORE_CR_MTX_RAM_ACCESS_STATUS_OFFSET (0x010C) 212 213 // MTX_CORE CR_MTX_RAM_ACCESS_STATUS MTX_MTX_MCM_STAT 214 #define MTX_CORE_CR_MTX_RAM_ACCESS_STATUS_MTX_MTX_MCM_STAT_MASK (0x00000001) 215 #define MTX_CORE_CR_MTX_RAM_ACCESS_STATUS_MTX_MTX_MCM_STAT_LSBMASK (0x00000001) 216 #define MTX_CORE_CR_MTX_RAM_ACCESS_STATUS_MTX_MTX_MCM_STAT_SHIFT (0) 217 218 #define MTX_CORE_CR_MTX_SOFT_RESET_OFFSET (0x0200) 219 220 // MTX_CORE CR_MTX_SOFT_RESET MTX_RESET 221 #define MTX_CORE_CR_MTX_SOFT_RESET_MTX_RESET_MASK (0x00000001) 222 #define MTX_CORE_CR_MTX_SOFT_RESET_MTX_RESET_LSBMASK (0x00000001) 223 #define MTX_CORE_CR_MTX_SOFT_RESET_MTX_RESET_SHIFT (0) 224 225 #define MTX_CORE_CR_MTX_SYSC_CDMAC_OFFSET (0x0340) 226 227 // MTX_CORE CR_MTX_SYSC_CDMAC BURSTSIZE 228 #define MTX_CORE_CR_MTX_SYSC_CDMAC_BURSTSIZE_MASK (0x07000000) 229 #define MTX_CORE_CR_MTX_SYSC_CDMAC_BURSTSIZE_LSBMASK (0x00000007) 230 #define MTX_CORE_CR_MTX_SYSC_CDMAC_BURSTSIZE_SHIFT (24) 231 232 // MTX_CORE CR_MTX_SYSC_CDMAC RNW 233 #define MTX_CORE_CR_MTX_SYSC_CDMAC_RNW_MASK (0x00020000) 234 #define MTX_CORE_CR_MTX_SYSC_CDMAC_RNW_LSBMASK (0x00000001) 235 #define MTX_CORE_CR_MTX_SYSC_CDMAC_RNW_SHIFT (17) 236 237 // MTX_CORE CR_MTX_SYSC_CDMAC ENABLE 238 #define MTX_CORE_CR_MTX_SYSC_CDMAC_ENABLE_MASK (0x00010000) 239 #define MTX_CORE_CR_MTX_SYSC_CDMAC_ENABLE_LSBMASK (0x00000001) 240 #define MTX_CORE_CR_MTX_SYSC_CDMAC_ENABLE_SHIFT (16) 241 242 // MTX_CORE CR_MTX_SYSC_CDMAC LENGTH 243 #define MTX_CORE_CR_MTX_SYSC_CDMAC_LENGTH_MASK (0x0000FFFF) 244 #define MTX_CORE_CR_MTX_SYSC_CDMAC_LENGTH_LSBMASK (0x0000FFFF) 245 #define MTX_CORE_CR_MTX_SYSC_CDMAC_LENGTH_SHIFT (0) 246 247 #define MTX_CORE_CR_MTX_SYSC_CDMAA_OFFSET (0x0344) 248 249 // MTX_CORE CR_MTX_SYSC_CDMAA CDMAA_ADDRESS 250 #define MTX_CORE_CR_MTX_SYSC_CDMAA_CDMAA_ADDRESS_MASK (0x03FFFFFC) 251 #define MTX_CORE_CR_MTX_SYSC_CDMAA_CDMAA_ADDRESS_LSBMASK (0x00FFFFFF) 252 #define MTX_CORE_CR_MTX_SYSC_CDMAA_CDMAA_ADDRESS_SHIFT (2) 253 254 #define MTX_CORE_CR_MTX_SYSC_CDMAS0_OFFSET (0x0348) 255 256 // MTX_CORE CR_MTX_SYSC_CDMAS0 COUNT 257 #define MTX_CORE_CR_MTX_SYSC_CDMAS0_COUNT_MASK (0xFFFF0000) 258 #define MTX_CORE_CR_MTX_SYSC_CDMAS0_COUNT_LSBMASK (0x0000FFFF) 259 #define MTX_CORE_CR_MTX_SYSC_CDMAS0_COUNT_SHIFT (16) 260 261 // MTX_CORE CR_MTX_SYSC_CDMAS0 RAMNUMBER 262 #define MTX_CORE_CR_MTX_SYSC_CDMAS0_RAMNUMBER_MASK (0x00000F00) 263 #define MTX_CORE_CR_MTX_SYSC_CDMAS0_RAMNUMBER_LSBMASK (0x0000000F) 264 #define MTX_CORE_CR_MTX_SYSC_CDMAS0_RAMNUMBER_SHIFT (8) 265 266 // MTX_CORE CR_MTX_SYSC_CDMAS0 DMAREQUEST 267 #define MTX_CORE_CR_MTX_SYSC_CDMAS0_DMAREQUEST_MASK (0x00000010) 268 #define MTX_CORE_CR_MTX_SYSC_CDMAS0_DMAREQUEST_LSBMASK (0x00000001) 269 #define MTX_CORE_CR_MTX_SYSC_CDMAS0_DMAREQUEST_SHIFT (4) 270 271 // MTX_CORE CR_MTX_SYSC_CDMAS0 DONOTHING 272 #define MTX_CORE_CR_MTX_SYSC_CDMAS0_DONOTHING_MASK (0x00000001) 273 #define MTX_CORE_CR_MTX_SYSC_CDMAS0_DONOTHING_LSBMASK (0x00000001) 274 #define MTX_CORE_CR_MTX_SYSC_CDMAS0_DONOTHING_SHIFT (0) 275 276 #define MTX_CORE_CR_MTX_SYSC_CDMAS1_OFFSET (0x034C) 277 278 // MTX_CORE CR_MTX_SYSC_CDMAS1 CDMAS1_ADDRESS 279 #define MTX_CORE_CR_MTX_SYSC_CDMAS1_CDMAS1_ADDRESS_MASK (0x03FFFFFC) 280 #define MTX_CORE_CR_MTX_SYSC_CDMAS1_CDMAS1_ADDRESS_LSBMASK (0x00FFFFFF) 281 #define MTX_CORE_CR_MTX_SYSC_CDMAS1_CDMAS1_ADDRESS_SHIFT (2) 282 283 #define MTX_CORE_CR_MTX_SYSC_CDMAT_OFFSET (0x0350) 284 285 // MTX_CORE CR_MTX_SYSC_CDMAT TRANSFERDATA 286 #define MTX_CORE_CR_MTX_SYSC_CDMAT_TRANSFERDATA_MASK (0xFFFFFFFF) 287 #define MTX_CORE_CR_MTX_SYSC_CDMAT_TRANSFERDATA_LSBMASK (0xFFFFFFFF) 288 #define MTX_CORE_CR_MTX_SYSC_CDMAT_TRANSFERDATA_SHIFT (0) 289 290 291 292 #ifdef __cplusplus 293 } 294 #endif 295 296 #endif /* __MSVDX_MTX_REG_IO2_H__ */ 297
