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      1 #define OFFSET_x86_EAX 8
      2 #define OFFSET_x86_EBX 20
      3 #define OFFSET_x86_ECX 12
      4 #define OFFSET_x86_EDX 16
      5 #define OFFSET_x86_ESI 32
      6 #define OFFSET_x86_EDI 36
      7 #define OFFSET_x86_EBP 28
      8 #define OFFSET_x86_ESP 24
      9 #define OFFSET_x86_EIP 68
     10 #define OFFSET_x86_CS 288
     11 #define OFFSET_x86_DS 290
     12 #define OFFSET_x86_ES 292
     13 #define OFFSET_x86_FS 294
     14 #define OFFSET_x86_GS 296
     15 #define OFFSET_x86_SS 298
     16 #define OFFSET_amd64_RAX 16
     17 #define OFFSET_amd64_RBX 40
     18 #define OFFSET_amd64_RCX 24
     19 #define OFFSET_amd64_RDX 32
     20 #define OFFSET_amd64_RSI 64
     21 #define OFFSET_amd64_RDI 72
     22 #define OFFSET_amd64_RSP 48
     23 #define OFFSET_amd64_RBP 56
     24 #define OFFSET_amd64_R8 80
     25 #define OFFSET_amd64_R9 88
     26 #define OFFSET_amd64_R10 96
     27 #define OFFSET_amd64_R11 104
     28 #define OFFSET_amd64_R12 112
     29 #define OFFSET_amd64_R13 120
     30 #define OFFSET_amd64_R14 128
     31 #define OFFSET_amd64_R15 136
     32 #define OFFSET_amd64_RIP 184
     33 #define OFFSET_ppc32_GPR0 16
     34 #define OFFSET_ppc32_GPR1 20
     35 #define OFFSET_ppc32_GPR2 24
     36 #define OFFSET_ppc32_GPR3 28
     37 #define OFFSET_ppc32_GPR4 32
     38 #define OFFSET_ppc32_GPR5 36
     39 #define OFFSET_ppc32_GPR6 40
     40 #define OFFSET_ppc32_GPR7 44
     41 #define OFFSET_ppc32_GPR8 48
     42 #define OFFSET_ppc32_GPR9 52
     43 #define OFFSET_ppc32_GPR10 56
     44 #define OFFSET_ppc32_CIA 1168
     45 #define OFFSET_ppc32_CR0_0 1185
     46 #define OFFSET_ppc64_GPR0 16
     47 #define OFFSET_ppc64_GPR1 24
     48 #define OFFSET_ppc64_GPR2 32
     49 #define OFFSET_ppc64_GPR3 40
     50 #define OFFSET_ppc64_GPR4 48
     51 #define OFFSET_ppc64_GPR5 56
     52 #define OFFSET_ppc64_GPR6 64
     53 #define OFFSET_ppc64_GPR7 72
     54 #define OFFSET_ppc64_GPR8 80
     55 #define OFFSET_ppc64_GPR9 88
     56 #define OFFSET_ppc64_GPR10 96
     57 #define OFFSET_ppc64_CIA 1296
     58 #define OFFSET_ppc64_CR0_0 1325
     59 #define OFFSET_arm_R0 8
     60 #define OFFSET_arm_R1 12
     61 #define OFFSET_arm_R2 16
     62 #define OFFSET_arm_R3 20
     63 #define OFFSET_arm_R4 24
     64 #define OFFSET_arm_R5 28
     65 #define OFFSET_arm_R7 36
     66 #define OFFSET_arm_R13 60
     67 #define OFFSET_arm_R14 64
     68 #define OFFSET_arm_R15T 68
     69 #define OFFSET_arm64_X0 16
     70 #define OFFSET_arm64_X1 24
     71 #define OFFSET_arm64_X2 32
     72 #define OFFSET_arm64_X3 40
     73 #define OFFSET_arm64_X4 48
     74 #define OFFSET_arm64_X5 56
     75 #define OFFSET_arm64_X6 64
     76 #define OFFSET_arm64_X7 72
     77 #define OFFSET_arm64_X8 80
     78 #define OFFSET_arm64_XSP 264
     79 #define OFFSET_arm64_PC 272
     80 #define OFFSET_s390x_r2 208
     81 #define OFFSET_s390x_r3 216
     82 #define OFFSET_s390x_r4 224
     83 #define OFFSET_s390x_r5 232
     84 #define OFFSET_s390x_r6 240
     85 #define OFFSET_s390x_r7 248
     86 #define OFFSET_s390x_r15 312
     87 #define OFFSET_s390x_IA 336
     88 #define OFFSET_s390x_SYSNO 344
     89 #define OFFSET_s390x_IP_AT_SYSCALL 408
     90 #define OFFSET_s390x_fpc 328
     91 #define OFFSET_s390x_CC_OP 352
     92 #define OFFSET_s390x_CC_DEP1 360
     93 #define OFFSET_s390x_CC_DEP2 368
     94 #define OFFSET_s390x_CC_NDEP 376
     95 #define OFFSET_mips32_r0 0
     96 #define OFFSET_mips32_r1 4
     97 #define OFFSET_mips32_r2 8
     98 #define OFFSET_mips32_r3 12
     99 #define OFFSET_mips32_r4 16
    100 #define OFFSET_mips32_r5 20
    101 #define OFFSET_mips32_r6 24
    102 #define OFFSET_mips32_r7 28
    103 #define OFFSET_mips32_r8 32
    104 #define OFFSET_mips32_r9 36
    105 #define OFFSET_mips32_r10 40
    106 #define OFFSET_mips32_r11 44
    107 #define OFFSET_mips32_r12 48
    108 #define OFFSET_mips32_r13 52
    109 #define OFFSET_mips32_r14 56
    110 #define OFFSET_mips32_r15 60
    111 #define OFFSET_mips32_r15 60
    112 #define OFFSET_mips32_r17 68
    113 #define OFFSET_mips32_r18 72
    114 #define OFFSET_mips32_r19 76
    115 #define OFFSET_mips32_r20 80
    116 #define OFFSET_mips32_r21 84
    117 #define OFFSET_mips32_r22 88
    118 #define OFFSET_mips32_r23 92
    119 #define OFFSET_mips32_r24 96
    120 #define OFFSET_mips32_r25 100
    121 #define OFFSET_mips32_r26 104
    122 #define OFFSET_mips32_r27 108
    123 #define OFFSET_mips32_r28 112
    124 #define OFFSET_mips32_r29 116
    125 #define OFFSET_mips32_r30 120
    126 #define OFFSET_mips32_r31 124
    127 #define OFFSET_mips32_PC 128
    128 #define OFFSET_mips32_HI 132
    129 #define OFFSET_mips32_LO 136
    130 #define OFFSET_mips64_r0 0
    131 #define OFFSET_mips64_r1 8
    132 #define OFFSET_mips64_r2 16
    133 #define OFFSET_mips64_r3 24
    134 #define OFFSET_mips64_r4 32
    135 #define OFFSET_mips64_r5 40
    136 #define OFFSET_mips64_r6 48
    137 #define OFFSET_mips64_r7 56
    138 #define OFFSET_mips64_r8 64
    139 #define OFFSET_mips64_r9 72
    140 #define OFFSET_mips64_r10 80
    141 #define OFFSET_mips64_r11 88
    142 #define OFFSET_mips64_r12 96
    143 #define OFFSET_mips64_r13 104
    144 #define OFFSET_mips64_r14 112
    145 #define OFFSET_mips64_r15 120
    146 #define OFFSET_mips64_r15 120
    147 #define OFFSET_mips64_r17 136
    148 #define OFFSET_mips64_r18 144
    149 #define OFFSET_mips64_r19 152
    150 #define OFFSET_mips64_r20 160
    151 #define OFFSET_mips64_r21 168
    152 #define OFFSET_mips64_r22 176
    153 #define OFFSET_mips64_r23 184
    154 #define OFFSET_mips64_r24 192
    155 #define OFFSET_mips64_r25 200
    156 #define OFFSET_mips64_r26 208
    157 #define OFFSET_mips64_r27 216
    158 #define OFFSET_mips64_r28 224
    159 #define OFFSET_mips64_r29 232
    160 #define OFFSET_mips64_r30 240
    161 #define OFFSET_mips64_r31 248
    162 #define OFFSET_mips64_PC 256
    163 #define OFFSET_mips64_HI 264
    164 #define OFFSET_mips64_LO 272
    165