| /external/llvm/lib/Target/XCore/Disassembler/ |
| XCoreDisassembler.cpp | 273 unsigned &Op3) {
283 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
552 unsigned Op1, Op2, Op3;
553 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
557 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
565 unsigned Op1, Op2, Op3;
566 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
570 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
578 unsigned Op1, Op2, Op3;
579 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 73 const MCOperand &Op3 = MI->getOperand(3);
77 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
80 switch (Op3.getImm()) {
113 if (Op2.isImm() && Op3.isImm()) {
117 int64_t imms = Op3.getImm();
147 if (Op2.getImm() > Op3.getImm()) {
150 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1;
158 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1;
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 221 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
226 N->getBasePtr(), Op2, Op3, N->getMemOperand(), N->getSuccessOrdering(),
[all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
