| /external/llvm/lib/Target/Mips/ |
| MipsAnalyzeImmediate.h | 43 /// GetInstSeqLsSLL - Get instruction sequences which end with a SLL to
50 /// ReplaceADDiuSLLWithLUi - Replace an ADDiu & SLL pair with a LUi.
58 unsigned ADDiu, ORi, SLL, LUi;
|
| MipsISelLowering.cpp | [all...] |
| /external/valgrind/main/none/tests/mips64/ |
| shift_instructions.c | 9 ROTR, ROTRV, SLL, SLLV,
159 case SLL:
160 TEST2("sll $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
161 TEST2("sll $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
162 TEST2("sll $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
163 TEST2("sll $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
164 TEST2("sll $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
165 TEST2("sll $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
166 TEST2("sll $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
167 TEST2("sll $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1)
[all...] |
| /external/linux-tools-perf/perf-3.12.0/arch/mips/lib/ |
| memcpy.S | 113 #define SLL dsll
148 #define SLL sll
328 SLL rem, len, 3 # rem = number of bits to keep
|
| /external/pcre/dist/sljit/ |
| sljitNativeMIPS_common.c | 165 #define SLL (HI(0) | LO(0))
189 #define SLL_W SLL
[all...] |
| sljitNativeSPARC_common.c | 150 #define SLL (OPC1(0x2) | OPC3(0x25))
170 #define SLL_W SLL
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.cpp | 397 case LSL: mMips->SLL(tmpReg, amode.reg, amode.value); break;
508 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break;
540 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break;
[all...] |
