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    Searched defs:isPPC64 (Results 1 - 9 of 9) sorted by null

  /external/llvm/lib/Target/PowerPC/MCTargetDesc/
PPCMCCodeEmitter.cpp 275 bool isPPC64 = TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le;
276 return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2);
PPCMCTargetDesc.cpp 52 bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
54 unsigned Flavour = isPPC64 ? 0 : 1;
55 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR;
71 bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
76 MAI = new PPCMCAsmInfoDarwin(isPPC64, TheTriple);
78 MAI = new PPCLinuxMCAsmInfo(isPPC64, TheTriple);
81 unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1;
  /external/llvm/lib/Target/PowerPC/
PPCAsmPrinter.cpp 308 bool isPPC64 = Subtarget.isPPC64();
480 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
499 TmpInst.setOpcode(isPPC64 ? PPC::LD : PPC::LWZ);
531 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
547 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
563 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
583 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
599 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
615 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC")
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PPCSubtarget.h 84 bool IsPPC64;
166 /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
168 bool isPPC64() const { return IsPPC64; }
PPCFrameLowering.cpp 49 if (Subtarget.isPPC64()) {
189 if (Subtarget.isPPC64()) {
385 (Subtarget.isPPC64() || // 32-bit SVR4, no stack-
402 unsigned minCallFrameSize = getLinkageSize(Subtarget.isPPC64(),
511 bool isPPC64 = Subtarget.isPPC64();
548 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
549 unsigned BPReg = isPPC64 ? PPC::X30 : PPC::R30;
550 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
551 unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR
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PPCISelDAGToDAG.cpp 749 bool isPPC64 = (PtrVT == MVT::i64);
766 if (isPPC64) break;
790 if (isPPC64) break;
799 if (isPPC64) break;
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PPCInstrInfo.cpp 341 bool isPPC64 = Subtarget.isPPC64();
398 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
409 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
467 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
481 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
547 bool isPPC64 = Subtarget.isPPC64();
555 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
556 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB)
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PPCISelLowering.cpp 74 bool isPPC64 = Subtarget.isPPC64();
75 setMinStackArgumentAlignment(isPPC64 ? 8:4);
103 if (isPPC64 || Subtarget.hasFPCVT()) {
106 isPPC64 ? MVT::i64 : MVT::i32);
109 isPPC64 ? MVT::i64 : MVT::i32);
300 if (isPPC64) {
319 if (Subtarget.isSVR4ABI() && !isPPC64)
362 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
629 if (isPPC64) {
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  /external/llvm/lib/Target/PowerPC/AsmParser/
PPCAsmParser.cpp 218 bool IsPPC64;
227 bool isPPC64() const { return IsPPC64; }
271 IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
302 bool IsPPC64;
335 IsPPC64 = o.IsPPC64;
358 /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
359 bool isPPC64() const { return IsPPC64; }
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