/art/compiler/dex/quick/ |
mir_to_lir.cc | 247 RegStorage r_result = rl_dest.reg; local 248 if (!RegClassMatches(reg_class, r_result)) { 249 r_result = wide ? AllocTypedTempWide(rl_dest.fp, reg_class) 253 LoadRefDisp(reg_obj, data.field_offset, r_result, data.is_volatile ? kVolatile : kNotVolatile); 255 LoadBaseDisp(reg_obj, data.field_offset, r_result, size, data.is_volatile ? kVolatile : 258 if (r_result.NotExactlyEquals(rl_dest.reg)) { 260 OpRegCopyWide(rl_dest.reg, r_result); 262 OpRegCopy(rl_dest.reg, r_result); [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv30/ |
nvfx_fragprog.c | 25 struct nvfx_reg r_result[PIPE_MAX_SHADER_OUTPUTS]; member in struct:nvfx_fpc 391 src.reg = fpc->r_result[fsrc->Register.Index]; 416 return fpc->r_result[fdst->Register.Index]; [all...] |
nvfx_vertprog.c | 48 struct nvfx_reg r_result[PIPE_MAX_SHADER_OUTPUTS]; member in struct:nvfx_vpc 427 dst = vpc->r_result[fdst->Register.Index]; 830 vpc->r_result[idx] = temp(vpc); 871 vpc->r_result[idx] = nvfx_reg(NVFXSR_NONE, 0); 884 vpc->r_result[idx] = nvfx_reg(NVFXSR_OUTPUT, hw); 1003 vpc->r_result[vpc->hpos_idx] = temp(vpc); [all...] |
/external/mesa3d/src/gallium/drivers/nv30/ |
nvfx_fragprog.c | 25 struct nvfx_reg r_result[PIPE_MAX_SHADER_OUTPUTS]; member in struct:nvfx_fpc 391 src.reg = fpc->r_result[fsrc->Register.Index]; 416 return fpc->r_result[fdst->Register.Index]; [all...] |
nvfx_vertprog.c | 48 struct nvfx_reg r_result[PIPE_MAX_SHADER_OUTPUTS]; member in struct:nvfx_vpc 427 dst = vpc->r_result[fdst->Register.Index]; 830 vpc->r_result[idx] = temp(vpc); 871 vpc->r_result[idx] = nvfx_reg(NVFXSR_NONE, 0); 884 vpc->r_result[idx] = nvfx_reg(NVFXSR_OUTPUT, hw); 1003 vpc->r_result[vpc->hpos_idx] = temp(vpc); [all...] |