| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 1 //==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
10 // This class prints an AArch64 MCInst to a .s file.
61 if (Opcode == AArch64::SYSxt)
68 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
69 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
75 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri);
76 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri)
[all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -------*- C++ -*-===//
27 #define DEBUG_TYPE "aarch64-disassembler"
257 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
258 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 1 //===- AArch64InstrInfo.cpp - AArch64 Instruction Information -------------===//
10 // This file contains the AArch64 implementation of the TargetInstrInfo class.
32 : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP),
42 if (MI->getOpcode() == AArch64::INLINEASM)
66 case AArch64::Bcc:
70 case AArch64::CBZW:
71 case AArch64::CBZX:
72 case AArch64::CBNZW:
73 case AArch64::CBNZX
[all...] |
| AArch64RegisterInfo.cpp | 1 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
10 // This file contains the AArch64 implementation of the TargetRegisterInfo
38 : AArch64GenRegisterInfo(AArch64::LR), TII(tii), STI(sti) {}
83 Reserved.set(AArch64::SP);
84 Reserved.set(AArch64::XZR);
85 Reserved.set(AArch64::WSP);
86 Reserved.set(AArch64::WZR);
89 Reserved.set(AArch64::FP);
90 Reserved.set(AArch64::W29);
94 Reserved.set(AArch64::X18); // Platform registe
[all...] |
| AArch64LoadStoreOptimizer.cpp | 1 //=- AArch64LoadStoreOptimizer.cpp - AArch64 load/store opt. pass -*- C++ -*-=//
32 #define DEBUG_TYPE "aarch64-ldst-opt"
43 static cl::opt<unsigned> ScanLimit("aarch64-load-store-scan-limit",
48 "aarch64-unscaled-mem-op", cl::Hidden,
49 cl::desc("Allow AArch64 unscaled load/store combining"), cl::init(true));
104 return "AArch64 load / store optimization pass";
117 case AArch64::STURSi:
119 case AArch64::STURDi:
121 case AArch64::STURQi:
123 case AArch64::STURWi
[all...] |
| AArch64ISelDAGToDAG.cpp | 1 //===-- AArch64ISelDAGToDAG.cpp - A dag to dag inst selector for AArch64 --===//
10 // This file defines an instruction selector for the AArch64 target.
28 #define DEBUG_TYPE "aarch64-isel"
31 /// AArch64DAGToDAGISel - AArch64 specific code to select AArch64 machine
52 return "AArch64 Instruction Selection";
218 // Require the address to be in a register. That is safe for all AArch64
429 /// SelectMLAV64LaneV128 - AArch64 supports vector MLAs where one multiplicand
459 MLAOpc = AArch64::MLAv4i16_indexed;
462 MLAOpc = AArch64::MLAv8i16_indexed
[all...] |
| AArch64BranchRelaxation.cpp | 1 //===-- AArch64BranchRelaxation.cpp - AArch64 branch relaxation -----------===//
12 #include "AArch64.h"
26 #define DEBUG_TYPE "aarch64-branch-relax"
29 BranchRelaxation("aarch64-branch-relax", cl::Hidden, cl::init(true),
33 TBZDisplacementBits("aarch64-tbz-offset-bits", cl::Hidden, cl::init(14),
37 CBZDisplacementBits("aarch64-cbz-offset-bits", cl::Hidden, cl::init(19),
41 BCCDisplacementBits("aarch64-bcc-offset-bits", cl::Hidden, cl::init(19),
100 return "AArch64 branch relaxation pass";
229 BuildMI(OrigBB, DebugLoc(), TII->get(AArch64::B)).addMBB(NewBB);
278 case AArch64::TBZW
[all...] |
| AArch64ConditionalCompares.cpp | 1 //===-- AArch64ConditionalCompares.cpp --- CCMP formation for AArch64 -----===//
20 #include "AArch64.h"
45 #define DEBUG_TYPE "aarch64-ccmp"
50 "aarch64-ccmp-limit", cl::init(30), cl::Hidden,
54 static cl::opt<bool> Stress("aarch64-stress-ccmp", cl::Hidden,
101 // instructions. The AArch64 conditional compare instructions have an immediate
260 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR)
285 case AArch64::CBZW:
286 case AArch64::CBZX
[all...] |
| AArch64ExpandPseudoInsts.cpp | 35 return "AArch64 pseudo instruction expansion pass";
98 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
100 .addReg(AArch64::XZR)
108 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
165 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
167 .addReg(AArch64::XZR)
185 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
210 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
348 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
350 .addReg(AArch64::XZR
[all...] |
| AArch64A53Fix835769.cpp | 18 #include "AArch64.h"
32 #define DEBUG_TYPE "aarch64-fix-cortex-a53-835769"
44 case AArch64::PRFMl:
45 case AArch64::PRFMroW:
46 case AArch64::PRFMroX:
47 case AArch64::PRFMui:
48 case AArch64::PRFUMi:
63 case AArch64::MSUBXrrr:
64 case AArch64::MADDXrrr:
65 case AArch64::SMADDLrrr
[all...] |
| AArch64FrameLowering.cpp | 1 //===- AArch64FrameLowering.cpp - AArch64 Frame Lowering -------*- C++ -*-====//
10 // This file contains the AArch64 implementation of TargetFrameLowering class.
36 static cl::opt<bool> EnableRedZone("aarch64-redzone",
37 cl::desc("enable use of redzone on AArch64"),
91 "No stack realignment on AArch64!");
142 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, Amount, TII);
148 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, -CalleePopAmount,
189 if (HasFP && (FramePtr == Reg || Reg == AArch64::LR))
[all...] |
| AArch64AdvSIMDScalarPass.cpp | 36 #include "AArch64.h"
50 #define DEBUG_TYPE "aarch64-simd-scalar"
55 TransformAll("aarch64-simd-scalar-force-all",
105 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass);
106 return AArch64::GPR64RegClass.contains(Reg);
112 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) &&
114 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) &&
115 SubReg == AArch64::dsub);
117 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) ||
118 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub)
[all...] |
| AArch64FastISel.cpp | 1 //===-- AArch6464FastISel.cpp - AArch64 FastISel implementation -----------===//
10 // This file defines the AArch64-specific support for the FastISel class. Some
16 #include "AArch64.h"
186 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
187 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
212 Opc = AArch64::FMOVDi;
215 Opc = AArch64::FMOVSi;
230 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
231 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
234 unsigned Opc = is64bit ? AArch64::LDRDui : AArch64::LDRSui
[all...] |
| AArch64AsmPrinter.cpp | 1 //===-- AArch64AsmPrinter.cpp - AArch64 LLVM assembly writer --------------===//
11 // of machine-dependent LLVM code to the AArch64 assembly language.
15 #include "AArch64.h"
61 return "AArch64 Assembly Printer";
261 RegToPrint, isVector ? AArch64::vreg : AArch64::NoRegAltName);
287 unsigned Reg = ExtraCode[0] == 'w' ? AArch64::WZR : AArch64::XZR;
302 RC = &AArch64::FPR8RegClass;
305 RC = &AArch64::FPR16RegClass
[all...] |
| Makefile | 1 ##===- lib/Target/AArch64/Makefile -------------------------*- Makefile -*-===##
12 TARGET = AArch64
|
| AArch64StorePairSuppress.cpp | 26 #define DEBUG_TYPE "aarch64-stp-suppress"
43 return "AArch64 Store Pair Suppression";
82 unsigned SCIdx = TII->get(AArch64::STPDi).getSchedClass();
111 case AArch64::STRSui:
112 case AArch64::STRDui:
113 case AArch64::STURSi:
114 case AArch64::STURDi:
|
| AArch64CollectLOH.cpp | 1 //===---------- AArch64CollectLOH.cpp - AArch64 collect LOH pass --*- C++ -*-=//
101 #include "AArch64.h"
125 #define DEBUG_TYPE "aarch64-collect-loh"
128 PreCollectRegister("aarch64-collect-loh-pre-collect-register", cl::Hidden,
134 BasicBlockScopeOnly("aarch64-collect-loh-bb-only", cl::Hidden,
180 return "AArch64 Collect Linker Optimization Hint (LOH)";
219 INITIALIZE_PASS_BEGIN(AArch64CollectLOH, "aarch64-collect-loh",
220 "AArch64 Collect Linker Optimization Hint (LOH)", false,
223 INITIALIZE_PASS_END(AArch64CollectLOH, "aarch64-collect-loh",
224 "AArch64 Collect Linker Optimization Hint (LOH)", false
[all...] |
| AArch64InstrInfo.h | 1 //===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
10 // This file contains the AArch64 implementation of the TargetInstrInfo class.
17 #include "AArch64.h"
208 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
212 case AArch64::Bcc:
213 case AArch64::CBZW:
214 case AArch64::CBZX:
215 case AArch64::CBNZW:
216 case AArch64::CBNZX:
217 case AArch64::TBZW
[all...] |
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.h | 1 //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
11 // the AArch64 target useful for the compiler back-end and the MC libraries.
22 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
31 case AArch64::X0: return AArch64::W0;
32 case AArch64::X1: return AArch64::W1;
33 case AArch64::X2: return AArch64::W2;
34 case AArch64::X3: return AArch64::W3
[all...] |
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AsmBackend.cpp | 1 //===-- AArch64AsmBackend.cpp - AArch64 Assembler Backend -----------------===//
10 #include "AArch64.h"
34 return AArch64::NumTargetFixupKinds;
38 const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = {
91 case AArch64::fixup_aarch64_tlsdesc_call:
98 case AArch64::fixup_aarch64_movw:
101 case AArch64::fixup_aarch64_pcrel_branch14:
102 case AArch64::fixup_aarch64_add_imm12:
103 case AArch64::fixup_aarch64_ldst_imm12_scale1:
104 case AArch64::fixup_aarch64_ldst_imm12_scale2
[all...] |
| AArch64FixupKinds.h | 1 //===-- AArch64FixupKinds.h - AArch64 Specific Fixup Entries ----*- C++ -*-===//
16 namespace AArch64 {
73 } // end namespace AArch64
|
| AArch64ELFObjectWriter.cpp | 1 //===-- AArch64ELFObjectWriter.cpp - AArch64 ELF Writer -------------------===//
70 case AArch64::fixup_aarch64_pcrel_adr_imm21:
73 case AArch64::fixup_aarch64_pcrel_adrp_imm21:
83 case AArch64::fixup_aarch64_pcrel_branch26:
85 case AArch64::fixup_aarch64_pcrel_call26:
87 case AArch64::fixup_aarch64_ldr_pcrel_imm19:
91 case AArch64::fixup_aarch64_pcrel_branch14:
93 case AArch64::fixup_aarch64_pcrel_branch19:
106 case AArch64::fixup_aarch64_add_imm12:
126 case AArch64::fixup_aarch64_ldst_imm12_scale1
[all...] |
| /external/llvm/host/include/llvm/Config/ |
| Targets.def | 29 LLVM_TARGET(AArch64)
|
| /frameworks/compile/mclinker/ |
| Android.mk | 27 # AArch64 Code Generation Libraries
29 lib/Target/AArch64 \
30 lib/Target/AArch64/TargetInfo
|
| /external/llvm/ |
| Android.mk | 54 # AArch64 Code Generation Libraries
56 lib/Target/AArch64 \
57 lib/Target/AArch64/AsmParser \
58 lib/Target/AArch64/InstPrinter \
59 lib/Target/AArch64/Disassembler \
60 lib/Target/AArch64/MCTargetDesc \
61 lib/Target/AArch64/TargetInfo \
62 lib/Target/AArch64/Utils
|
