| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AddressingModes.h | 25 /// AArch64_AM - AArch64 Addressing Mode Stuff
26 namespace AArch64_AM {
52 static inline const char *getShiftExtendName(AArch64_AM::ShiftExtendType ST) {
55 case AArch64_AM::LSL: return "lsl";
56 case AArch64_AM::LSR: return "lsr";
57 case AArch64_AM::ASR: return "asr";
58 case AArch64_AM::ROR: return "ror";
59 case AArch64_AM::MSL: return "msl";
60 case AArch64_AM::UXTB: return "uxtb";
61 case AArch64_AM::UXTH: return "uxth"
[all...] |
| AArch64MCCodeEmitter.cpp | 280 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL &&
282 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm());
569 unsigned ShiftVal = AArch64_AM::getShiftValue(MO.getImm());
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 226 AArch64_AM::ShiftExtendType Type;
391 AArch64_AM::ShiftExtendType getShiftExtendType() const {
626 return AArch64_AM::isLogicalImmediate(Val, 32);
634 return AArch64_AM::isLogicalImmediate(MCE->getValue(), 64);
643 return AArch64_AM::isLogicalImmediate(Val, 32);
651 return AArch64_AM::isLogicalImmediate(~MCE->getValue(), 64);
699 return AArch64_AM::isAdvSIMDModImmType10(MCE->getValue());
941 AArch64_AM::ShiftExtendType ST = getShiftExtendType();
942 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR |
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ExpandPseudoInsts.cpp | 95 if (AArch64_AM::processLogicalImmediate(OrrImm, 64, Encoding)) {
112 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt));
127 return AArch64_AM::processLogicalImmediate(Chunk, 64, Encoding);
190 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt));
214 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt));
346 AArch64_AM::processLogicalImmediate(OrrImm, 64, Encoding);
365 AArch64_AM::getShifterImm(AArch64_AM::LSL, FirstMovkIdx * 16))
[all...] |
| AArch64ISelDAGToDAG.cpp | 249 unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt);
289 static AArch64_AM::ShiftExtendType getShiftTypeForNode(SDValue N) {
292 return AArch64_AM::InvalidShiftExtend;
294 return AArch64_AM::LSL;
296 return AArch64_AM::LSR;
298 return AArch64_AM::ASR;
300 return AArch64_AM::ROR;
320 AArch64_AM::ShiftExtendType ShType = getShiftTypeForNode(N);
321 if (ShType == AArch64_AM::InvalidShiftExtend
[all...] |
| AArch64InstrInfo.cpp | 484 AArch64_AM::encodeLogicalImmediate(1ull << Cond[3].getImm(), 32));
489 AArch64_AM::encodeLogicalImmediate(1ull << Cond[3].getImm(), 64));
652 CmpValue = AArch64_AM::decodeLogicalImmediate(
[all...] |
| AArch64ISelLowering.cpp | [all...] |
| AArch64RegisterInfo.cpp | 298 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
|
| AArch64FastISel.cpp | 211 Imm = AArch64_AM::getFP64Imm(Val);
214 Imm = AArch64_AM::getFP32Imm(Val);
590 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
679 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
803 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
[all...] |
| AArch64LoadStoreOptimizer.cpp | 533 assert(AArch64_AM::getShiftValue(Update->getOperand(3).getImm()) == 0 &&
576 assert(AArch64_AM::getShiftValue(Update->getOperand(3).getImm()) == 0 &&
621 if (AArch64_AM::getShiftValue(MI->getOperand(3).getImm()))
[all...] |
| AArch64TargetTransformInfo.cpp | 146 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, 64))
|
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | [all...] |
