/external/pcre/dist/sljit/ |
sljitNativePPC_64.c | 52 return push_inst(compiler, ADDI | D(reg) | A(0) | IMM(imm)); 70 FAIL_IF(push_inst(compiler, ADDI | D(reg) | A(0) | IMM(tmp >> 48))); 87 FAIL_IF(push_inst(compiler, ADDI | D(reg) | A(0) | IMM(tmp >> 48))); 93 FAIL_IF(push_inst(compiler, ADDI | D(reg) | A(0) | IMM(tmp >> 48))); 103 FAIL_IF(push_inst(compiler, ADDI | D(reg) | A(0) | IMM(tmp >> 48))); 220 return push_inst(compiler, ADDI | D(dst) | A(src1) | compiler->imm); 234 FAIL_IF(push_inst(compiler, ADDI | D(dst) | A(src1) | (compiler->imm & 0xffff)));
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sljitNativePPC_32.c | 32 return push_inst(compiler, ADDI | D(reg) | A(0) | IMM(imm)); 101 return push_inst(compiler, ADDI | D(dst) | A(src1) | compiler->imm); 114 FAIL_IF(push_inst(compiler, ADDI | D(dst) | A(src1) | (compiler->imm & 0xffff)));
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sljitNativeARM_64.c | 68 #define ADDI 0x91000000 566 return push_inst(compiler, ((op == SLJIT_ADD ? ADDI : SUBI) ^ inv_bits) | RD(dst) | RN(reg)); 570 return push_inst(compiler, (ADDI ^ inv_bits) | RD(dst) | RN(reg) | (imm << 10)); 579 return push_inst(compiler, (ADDI ^ inv_bits) | RD(dst) | RN(reg) | ((imm >> 12) << 10) | (1 << 22)); 586 FAIL_IF(push_inst(compiler, (ADDI ^ inv_bits) | RD(dst) | RN(reg) | ((imm >> 12) << 10) | (1 << 22))); 587 return push_inst(compiler, (ADDI ^ inv_bits) | RD(dst) | RN(dst) | ((imm & 0xfff) << 10)); 814 return push_inst(compiler, ADDI | RD(dst) | RN(reg) | (value << 10)); 816 return push_inst(compiler, ADDI | (1 << 22) | RD(dst) | RN(reg) | (value >> 2)); 932 FAIL_IF(push_inst(compiler, ADDI | RD(other_r) | RN(other_r) | ((argw & 0xfff) << 10))); 934 FAIL_IF(push_inst(compiler, ADDI | (1 << 22) | RD(other_r) | RN(other_r) | ((argw >> 12) << 10))) [all...] |
sljitNativePPC_common.c | 135 #define ADDI (HI(14)) 615 FAIL_IF(push_inst(compiler, ADDI | D(TMP_ZERO) | A(0) | 0)); 676 FAIL_IF(push_inst(compiler, ADDI | D(SLJIT_SP) | A(SLJIT_SP) | IMM(compiler->local_size))); 952 FAIL_IF(push_inst(compiler, ADDI | D(TMP_REG3) | A(TMP_REG3) | (imm & 0x3))); \ [all...] |
/external/chromium_org/v8/src/mips/ |
constants-mips.cc | 290 // 16 bits Immediate type instructions. e.g.: addi dest, src, imm16. 296 case ADDI:
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constants-mips.h | 324 ADDI = ((1 << 3) + 0) << kOpcodeShift,
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simulator-mips.cc | [all...] |
assembler-mips.cc | [all...] |
/external/chromium_org/v8/src/mips64/ |
constants-mips64.cc | 307 // 16 bits Immediate type instructions. e.g.: addi dest, src, imm16. 313 case ADDI:
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constants-mips64.h | 289 ADDI = ((1 << 3) + 0) << kOpcodeShift,
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assembler-mips64.cc | [all...] |
simulator-mips64.cc | [all...] |
/external/valgrind/main/none/tests/mips64/ |
arithmetic_instruction.c | 6 ADD=0, ADDI, ADDIU, ADDU, 35 case ADDI: 39 TEST2("addi $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1); 40 TEST2("addi $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3); 41 TEST2("addi $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1); 42 TEST2("addi $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1);
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/external/llvm/lib/Target/PowerPC/ |
PPCRegisterInfo.cpp | 71 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 267 /// addi R0, SP, \#frameSize ; get the address of the previous frame 269 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 300 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 308 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 373 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 813 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 [all...] |
PPCFastISel.cpp | 378 // instead of "addi ry, r1, offset / ld rx, 0(ry)". Obj will [all...] |
PPCISelDAGToDAG.cpp | 807 SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op, [all...] |
PPCFrameLowering.cpp | 865 : PPC::ADDI ); [all...] |
/external/llvm/lib/Target/PowerPC/AsmParser/ |
PPCAsmParser.cpp | 657 TmpInst.setOpcode(PPC::ADDI); [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
DAGCombiner.cpp | [all...] |