/external/vixl/src/a64/ |
assembler-a64.cc | 884 VIXL_ASSERT(AreSameSizeAndType(rd, rn, rm)); 900 VIXL_ASSERT(AreSameSizeAndType(rd, rn, rm)); 1052 VIXL_ASSERT(AreSameSizeAndType(rt, rt2)); 1094 VIXL_ASSERT(AreSameSizeAndType(rt, rt2)); [all...] |
macro-assembler-a64.cc | 758 VIXL_ASSERT(AreSameSizeAndType(src0, src1, src2, src3)); 775 VIXL_ASSERT(AreSameSizeAndType(dst0, dst1, dst2, dst3)); 858 VIXL_ASSERT(AreSameSizeAndType(src0, src1, src2, src3)); 898 VIXL_ASSERT(AreSameSizeAndType(dst0, dst1, dst2, dst3)); [all...] |
assembler-a64.h | 291 // AreSameSizeAndType returns true if all of the specified registers have the 295 bool AreSameSizeAndType(const CPURegister& reg1, 314 VIXL_ASSERT(AreSameSizeAndType(reg1, reg2, reg3, reg4)); [all...] |
/external/chromium_org/v8/src/arm64/ |
assembler-arm64-inl.h | 913 DCHECK(AreSameSizeAndType(rt, rt2)); 937 DCHECK(AreSameSizeAndType(rt, rt2)); 950 DCHECK(AreSameSizeAndType(rt, rt2)); 963 DCHECK(AreSameSizeAndType(rt, rt2)); [all...] |
assembler-arm64.cc | 256 bool AreSameSizeAndType(const CPURegister& reg1, const CPURegister& reg2, [all...] |
macro-assembler-arm64.cc | 846 DCHECK(AreSameSizeAndType(rd, rm)); 870 DCHECK(AreSameSizeAndType(src0, src1, src2, src3)); 884 DCHECK(AreSameSizeAndType(src0, src1, src2, src3, src4, src5, src6, src7)); 900 DCHECK(AreSameSizeAndType(dst0, dst1, dst2, dst3)); [all...] |
assembler-arm64.h | 427 // AreSameSizeAndType returns true if all of the specified registers have the 431 bool AreSameSizeAndType(const CPURegister& reg1, 454 DCHECK(AreSameSizeAndType(reg1, reg2, reg3, reg4)); [all...] |