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Searched
refs:Arm64Mir2Lir
(Results
1 - 7
of
7
) sorted by null
/art/compiler/dex/quick/arm64/
utility_arm64.cc
26
int32_t
Arm64Mir2Lir
::EncodeImmSingle(uint32_t bits) {
58
int32_t
Arm64Mir2Lir
::EncodeImmDouble(uint64_t bits) {
90
size_t
Arm64Mir2Lir
::GetLoadStoreSize(LIR* lir) {
99
size_t
Arm64Mir2Lir
::GetInstructionOffset(LIR* lir) {
110
LIR*
Arm64Mir2Lir
::LoadFPConstantValue(RegStorage r_dest, int32_t value) {
134
LIR*
Arm64Mir2Lir
::LoadFPConstantValueWide(RegStorage r_dest, int64_t value) {
180
* @note This is the inverse of
Arm64Mir2Lir
::DecodeLogicalImmediate().
182
int
Arm64Mir2Lir
::EncodeLogicalImmediate(bool is_wide, uint64_t value) {
309
bool
Arm64Mir2Lir
::InexpensiveConstantInt(int32_t value) {
315
bool
Arm64Mir2Lir
::InexpensiveConstantFloat(int32_t value)
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...]
target_arm64.cc
85
RegLocation
Arm64Mir2Lir
::LocCReturn() {
89
RegLocation
Arm64Mir2Lir
::LocCReturnRef() {
93
RegLocation
Arm64Mir2Lir
::LocCReturnWide() {
97
RegLocation
Arm64Mir2Lir
::LocCReturnFloat() {
101
RegLocation
Arm64Mir2Lir
::LocCReturnDouble() {
106
RegStorage
Arm64Mir2Lir
::TargetReg(SpecialTargetRegister reg) {
144
ResourceMask
Arm64Mir2Lir
::GetRegMaskCommon(const RegStorage& reg) const {
158
ResourceMask
Arm64Mir2Lir
::GetPCUseDefEncoding() const {
166
void
Arm64Mir2Lir
::SetupTargetResourceMasks(LIR* lir, uint64_t flags,
188
ArmConditionCode
Arm64Mir2Lir
::ArmConditionEncoding(ConditionCode ccode)
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all
...]
fp_arm64.cc
24
void
Arm64Mir2Lir
::GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest,
66
void
Arm64Mir2Lir
::GenArithOpDouble(Instruction::Code opcode,
119
void
Arm64Mir2Lir
::GenConversion(Instruction::Code opcode,
201
void
Arm64Mir2Lir
::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias,
251
void
Arm64Mir2Lir
::GenCmpFP(Instruction::Code opcode, RegLocation rl_dest,
309
void
Arm64Mir2Lir
::GenNegFloat(RegLocation rl_dest, RegLocation rl_src) {
317
void
Arm64Mir2Lir
::GenNegDouble(RegLocation rl_dest, RegLocation rl_src) {
344
bool
Arm64Mir2Lir
::GenInlinedAbsFloat(CallInfo* info) {
362
bool
Arm64Mir2Lir
::GenInlinedAbsDouble(CallInfo* info) {
380
bool
Arm64Mir2Lir
::GenInlinedSqrt(CallInfo* info)
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...]
call_arm64.cc
46
void
Arm64Mir2Lir
::GenLargeSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) {
98
void
Arm64Mir2Lir
::GenLargePackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) {
159
void
Arm64Mir2Lir
::GenFillArrayData(uint32_t table_offset, RegLocation rl_src) {
188
void
Arm64Mir2Lir
::GenMonitorEnter(int opt_flags, RegLocation rl_src) {
237
void
Arm64Mir2Lir
::GenMonitorExit(int opt_flags, RegLocation rl_src) {
279
void
Arm64Mir2Lir
::GenMoveException(RegLocation rl_dest) {
290
void
Arm64Mir2Lir
::MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) {
305
void
Arm64Mir2Lir
::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) {
416
void
Arm64Mir2Lir
::GenExitSequence() {
432
void
Arm64Mir2Lir
::GenSpecialExitSequence()
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...]
int_arm64.cc
29
LIR*
Arm64Mir2Lir
::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) {
34
LIR*
Arm64Mir2Lir
::OpIT(ConditionCode ccode, const char* guide) {
39
void
Arm64Mir2Lir
::OpEndIT(LIR* it) {
49
void
Arm64Mir2Lir
::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1,
63
void
Arm64Mir2Lir
::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest,
91
void
Arm64Mir2Lir
::GenSelect(int32_t true_val, int32_t false_val, ConditionCode ccode,
175
void
Arm64Mir2Lir
::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
183
void
Arm64Mir2Lir
::GenSelect(BasicBlock* bb, MIR* mir) {
214
void
Arm64Mir2Lir
::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) {
259
LIR*
Arm64Mir2Lir
::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value
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...]
assemble_arm64.cc
105
const ArmEncodingMap
Arm64Mir2Lir
::EncodingMap[kA64Last] = {
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...]
codegen_arm64.h
27
class
Arm64Mir2Lir
FINAL : public Mir2Lir {
63
Arm64Mir2Lir
(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
Completed in 335 milliseconds