| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 528 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in
532 BR_CC,
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 58 BR_CC,
|
| MSP430ISelLowering.cpp | 106 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
107 setOperationAction(ISD::BR_CC, MVT::i16, Custom);
194 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 36 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
249 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
|
| SIISelLowering.cpp | 47 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
265 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 36 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
249 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
|
| SIISelLowering.cpp | 47 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
265 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 142 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
143 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
144 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
145 setOperationAction(ISD::BR_CC, MVT::i8, Expand);
146 setOperationAction(ISD::BR_CC, MVT::i16, Expand);
147 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
148 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 262 case ISD::BR_CC: return "br_cc";
|
| LegalizeDAG.cpp | [all...] |
| LegalizeFloatTypes.cpp | 627 case ISD::BR_CC: Res = SoftenFloatOp_BR_CC(N); break;
[all...] |
| LegalizeIntegerTypes.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 291 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
292 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
293 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
294 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 129 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
130 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
131 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
132 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
176 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
410 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 451 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
452 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
453 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
454 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
455 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
456 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
457 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 69 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
70 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
[all...] |
| AMDGPUISelLowering.cpp | 230 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | [all...] |
| PPCISelLowering.cpp | 643 setTargetDAGCombine(ISD::BR_CC);
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 93 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 130 // Lower SELECT_CC and BR_CC into separate comparisons and branches.
132 setOperationAction(ISD::BR_CC, VT, Custom);
140 // Expand BRCOND into a BR_CC (see above).
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
