| /external/llvm/lib/Target/X86/ |
| X86PadShortFunction.cpp | 42 // Cycles - Number of cycles until return if HasReturn is true, otherwise
43 // number of cycles until end of the BB
44 unsigned int Cycles;
46 VisitedBBInfo() : HasReturn(false), Cycles(0) {}
47 VisitedBBInfo(bool HasReturn, unsigned int Cycles)
48 : HasReturn(HasReturn), Cycles(Cycles) {}
64 unsigned int Cycles = 0);
67 unsigned int &Cycles);
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCSchedule.h | 41 // fixed number of cycles after dispatch. If a resource is unbuffered, then
54 /// scheduling class for the specified number of cycles.
57 unsigned Cycles;
60 return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles;
64 /// Specify the latency in cpu cycles for a particular scheduling class and def
70 int Cycles;
74 return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID;
78 /// Specify the number of cycles allowed after instruction issue before
[all...] |
| MCSubtargetInfo.h | 42 const unsigned *OperandCycles; // Itinerary operand cycles
123 return I->Cycles;
|
| /external/llvm/lib/CodeGen/ |
| TargetSchedule.cpp | 96 static unsigned capLatency(int Cycles) {
97 return Cycles >= 0 ? Cycles : 1000;
195 unsigned Latency = capLatency(WLEntry->Cycles);
246 Latency = std::max(Latency, capLatency(WLEntry->Cycles));
|
| MachineTraceMetrics.cpp | 96 // Add up per-processor resource cycles as well.
118 PRCycles[PI->ProcResourceIdx] += PI->Cycles;
123 // Scale the resource cycles so they are comparable.
332 // Ignore cycles that aren't natural loops.
362 // Ignore cycles that aren't natural loops.
453 // To is a new block. Mark the block as visited in case the CFG has cycles
572 Cycles.erase(&I);
774 unsigned Len = LIR.Height + Cycles[DefMI].Depth;
848 unsigned DepCycle = Cycles.lookup(Dep.DefMI).Depth;
[all...] |
| MachineScheduler.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineTraceMetrics.h | 36 // cycles required to execute the trace when execution is limited by data
38 // of cycles required to execute all instructions in the trace when ignoring
41 // Every instruction in the current block has a slack - the number of cycles
110 /// Get the scaled number of cycles used per processor resource in MBB.
206 /// Critical path length. This is the number of cycles in the longest data
228 /// Minimum number of cycles from this instruction is issued to the of the
252 /// This is the number of cycles required to execute all instructions from
258 /// Return the resource length of the trace. This is the number of cycles
278 return TE.Cycles.lookup(MI);
281 /// Return the slack of MI. This is the number of cycles MI can be delaye
[all...] |
| MachineScheduler.h | 581 /// Number of cycles it takes to issue the instructions scheduled in this
651 /// Number of cycles to issue the instructions scheduled in this zone.
664 /// Get the number of latency cycles "covered" by the scheduled
666 /// and the number of cycles required to issue the instructions.
704 unsigned getNextResourceCycle(unsigned PIdx, unsigned Cycles);
722 unsigned countResource(unsigned PIdx, unsigned Cycles, unsigned ReadyCycle);
|
| /external/oprofile/events/i386/westmere/ |
| events | 11 event:0x04 counters:0,1,2,3 um:x07 minimum:200000 name:SB_DRAIN : All Store buffer stall cycles
23 event:0x14 counters:0,1,2,3 um:arith minimum:2000000 name:ARITH : Cycles the divider is busy
27 event:0x1e counters:0,1,2,3 um:x01 minimum:2000000 name:INST_QUEUE_WRITE_CYCLES : Cycles instructions are written to the instruction queue
34 event:0x3c counters:0,1,2,3 um:cpu_clk_unhalted minimum:100000 name:CPU_CLK_UNHALTED : Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)
38 event:0x4f counters:0,1,2,3 um:x10 minimum:2000000 name:EPT : Extended Page Table walk cycles
42 event:0x63 counters:0,1 um:cache_lock_cycles minimum:2000000 name:CACHE_LOCK_CYCLES : Cycles L1D locked
44 event:0x80 counters:0,1,2,3 um:l1i minimum:2000000 name:L1I : L1I instruction fetch stall cycles
47 event:0x87 counters:0,1,2,3 um:ild_stall minimum:2000000 name:ILD_STALL : Any Instruction Length Decoder stall cycles
50 event:0xa2 counters:0,1,2,3 um:resource_stalls minimum:2000000 name:RESOURCE_STALLS : Resource related stall cycles
53 event:0xa8 counters:0,1,2,3 um:x01 minimum:2000000 name:LSD : Cycles when uops were delivered by the LS
[all...] |
| unit_masks | 19 0x01 cycles_div_busy Cycles the divider is busy
58 0x01 l1d_l2 Cycles L1D and L2 locked
59 0x02 l1d Cycles L1D locked
61 0x00 thread_p Cycles when thread is not halted (programmable counter)
62 0x01 ref_p Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)
66 0x04 walk_cycles DTLB load miss page walk cycles
73 0x04 walk_cycles DTLB miss page walk cycles
95 0x01 lcp Length Change Prefix stall cycles
96 0x02 mru Stall cycles due to BPU MRU bypass
97 0x04 iq_full Instruction Queue full stall cycles
[all...] |
| /external/llvm/utils/TableGen/ |
| SubtargetEmitter.cpp | 90 void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
306 // Form string as ,{ cycles, u1 | u2 | ... | un, timeinc, kind }
307 int Cycles = Stage->getValueAsInt("Cycles");
308 ItinString += " { " + itostr(Cycles) + ", ";
335 // number of operands that has cycles specified.
436 // operand cycles, and pipepine bypess tables. Then add the new Itinerary
487 // Emit as { cycles, u1 | u2 | ... | un, timeinc }, // indices
535 // Closing operand cycles
536 OperandCycleTable += " 0 // End operand cycles\n"
[all...] |
| /external/oprofile/events/i386/atom/ |
| events | 5 event:0x3c counters:0,1 um:cpu_clk_unhalted minimum:6000 name:CPU_CLK_UNHALTED : Clock cycles when not halted
6 event:0x3c counters:0,1 um:one minimum:6000 name:UNHALTED_REFERENCE_CYCLES : Unhalted reference cycles
22 event:0x14 counters:0,1 um:one minimum:6000 name:CYCLES_DIV_BUSY : Cycles the driver is busy
23 event:0x21 counters:0,1 um:core minimum:6000 name:CORE : Cycles L2 address bus is in use
24 event:0x22 counters:0,1 um:core minimum:6000 name:L2_DBUS_BUSY : Cycles the L2 cache data bus is busy
35 event:0x32 counters:0,1 um:core minimum:6000 name:L2_NO_REQ : Cycles no L2 cache requests are pending
41 event:0x62 counters:0,1 um:agent minimum:6000 name:BUS_DRDY_CLOCKS : Bus cycles when data is sent on the bus
42 event:0x63 counters:0,1 um:core,agent minimum:6000 name:BUS_LOCK_CLOCKS : Bus cycles when a LOCK signal is asserted.
43 event:0x64 counters:0,1 um:core minimum:6000 name:BUS_DATA_RCV : Bus cycles while processor receives data
70 event:0xC6 counters:0,1 um:cycles_int_masked minimum:6000 name:CYCLES_INT_MASKED : Cycles during which interrupts are disable
[all...] |
| unit_masks | 20 0x03 cycles Duration of page-walks in core cycles
36 0x00 core_p Core cycles when core is not halted
37 0x01 bus Bus cycles when core is not halted
38 0x02 no_other Bus cycles when core is active and the other is halted
82 0x01 cycles_int_masked Cycles during which interrupts are disabled
83 0x02 cycles_int_pending_and_masked Cycles during which interrupts are pending and disabled
|
| /external/oprofile/events/x86-64/family11h/ |
| events | 25 event:0x01 counters:0,1,2,3 um:zero minimum:500 name:CYCLES_NO_FPU_OPS_RETIRED : Cycles in which the FPU is empty
32 event:0x23 counters:0,1,2,3 um:zero minimum:500 name:LS_BUFFER_2_FULL_CYCLES : Cycles LS Buffer 2 full
78 event:0x76 counters:0,1,2,3 um:zero minimum:3000 name:CPU_CLK_UNHALTED : Cycles outside of halt state
94 event:0xcd counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES : Cycles with interrupts masked (IF=0)
95 event:0xce counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING : Cycles with interrupts masked while interrupt pending
128 event:0x1e9 counters:0,1,2,3 um:sideband_signals_and_special_cycles minimum:500 name:SIDEBAND_SIGNALS_AND_SPECIAL_CYCLES : Sideband Signals and Special Cycles
|
| /external/oprofile/events/mips/5K/ |
| events | 8 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : Cycles
|
| /external/oprofile/events/mips/34K/ |
| events | 14 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : 0-0 Cycles
36 event:0x12 counters:0 um:zero minimum:500 name:ALL_STALLS : 18-0 Stall cycles, including ALU and IFU
42 event:0x18 counters:0 um:zero minimum:500 name:CACHE_FIXUP_CYCLES : 24-0 Cache fixup cycles (specific to the 34K family microarchitecture)
43 event:0x19 counters:0 um:zero minimum:500 name:IFU_STALLS : 25-0 IFU stall cycles
57 # Count number of cycles (most often ``stall cycles'', ie time lost), not just number of events.
59 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
61 event:0x27 counters:0 um:zero minimum:500 name:DCACHE_MISS_CYCLES : 39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipeline
62 event:0x28 counters:0 um:zero minimum:500 name:UNCACHED_STALLS : 40-0 Uncached stall cycles
[all...] |
| /external/oprofile/events/x86-64/hammer/ |
| events | 23 event:0x01 counters:0,1,2,3 um:zero minimum:500 name:CYCLES_NO_FPU_OPS_RETIRED : Cycles with no FPU ops retired
30 event:0x23 counters:0,1,2,3 um:zero minimum:500 name:LS_BUFFER_2_FULL_CYCLES : Cycles LS Buffer 2 full
58 event:0x76 counters:0,1,2,3 um:zero minimum:3000 name:CPU_CLK_UNHALTED : Cycles outside of halt state
89 event:0xcd counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES : Cycles with interrupts masked (IF=0)
90 event:0xce counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING : Cycles with interrupts masked while interrupt pending
|
| /external/oprofile/events/mips/24K/ |
| events | 14 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : 0-0 Cycles
36 event:0x12 counters:0 um:zero minimum:500 name:ALL_STALLS : 18-0 Stall cycles, including ALU and IFU
42 event:0x18 counters:0 um:zero minimum:500 name:CACHE_FIXUP_CYCLES : 24-0 Cache fixup cycles (specific to the 24K family microarchitecture)
43 event:0x19 counters:0 um:zero minimum:500 name:IFU_STALLS : 25-0 IFU stall cycles
53 # Count number of cycles (most often ``stall cycles'', ie time lost), not just number of events.
55 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
56 event:0x26 counters:0 um:zero minimum:500 name:SYNC_STALLS : 38-0 SYNC stall cycles
57 event:0x27 counters:0 um:zero minimum:500 name:DCACHE_MISS_CYCLES : 39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipelin
[all...] |
| /external/oprofile/events/mips/1004K/ |
| events | 14 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : 0-0 Cycles
36 event:0x12 counters:0 um:zero minimum:500 name:ALL_STALLS : 18-0 Stall cycles, including ALU and IFU
42 event:0x18 counters:0 um:zero minimum:500 name:CACHE_FIXUP_CYCLES : 24-0 Cache fixup cycles (specific to the 34K family microarchitecture)
43 event:0x19 counters:0 um:zero minimum:500 name:IFU_STALLS : 25-0 IFU stall cycles
55 event:0x24 counters:0 um:zero minimum:500 name:INTERVENTION_STALLS : 36-0 Cache coherence intervention processing stall cycles
58 # Count number of cycles (most often ``stall cycles'', ie time lost), not just number of events.
60 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
62 event:0x27 counters:0 um:zero minimum:500 name:DCACHE_MISS_CYCLES : 39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipelin
[all...] |
| /external/oprofile/events/mips/74K/ |
| events | 14 event:0x0 counters:0,1,2,3 um:zero minimum:500 name:CYCLES : 0-0 Cycles
21 event:0x3 counters:0,2 um:zero minimum:500 name:REDIRECT_STALLS : 3-0 Stall cycles due to register indirect jumps (including non-predicted JR $31), ERET/WAIT instructions, and IFU determined exception
25 event:0x7 counters:0,2 um:zero minimum:500 name:ICACHE_MISS_STALLS : 7-0 Instruction cache miss stall cycles
26 event:0x8 counters:0,2 um:zero minimum:500 name:UNCACHED_IFETCH_STALLS : 8-0 Uncached instruction fetch stall cycles
29 event:0xb counters:0,2 um:zero minimum:500 name:IFU_IDU_MISS_PRED_UPSTREAM_CYCLES : 11-0 Cycles IFU-IDU gate is closed (to prevent upstream from getting ahead) due to mispredicted branch
30 event:0xc counters:0,2 um:zero minimum:500 name:IFU_IDU_CLOGED_DOWNSTREAM_CYCLES : 12-0 Cycles IFU-IDU gate is closed (waiting for downstream to unclog) due to MTC0/MFC0 sequence in pipe, EHB, or blocked DD, DR, or DS
31 event:0xd counters:0,2 um:zero minimum:500 name:DDQ0_FULL_DR_STALLS : 13-0 DR stage stall cycles due to DDQ0 (ALU out-of-order dispatch queue) full
32 event:0xe counters:0,2 um:zero minimum:500 name:ALCB_FULL_DR_STALLS : 14-0 DR stage stall cycles due to ALCB (ALU completion buffers) full
33 event:0xf counters:0,2 um:zero minimum:500 name:CLDQ_FULL_DR_STALLS : 15-0 DR stage stall cycles due to CLDQ (data comming back from FPU) ful
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600InstrInfo.cpp | 422 unsigned Cycles[3] = { 2, 1, 0};
423 return Cycles[Op];
426 unsigned Cycles[3] = { 1, 2, 2};
427 return Cycles[Op];
430 unsigned Cycles[3] = { 2, 1, 2};
431 return Cycles[Op];
434 unsigned Cycles[3] = { 2, 2, 1};
435 return Cycles[Op];
[all...] |
| /external/oprofile/events/mips/r10000/ |
| events | 6 event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Cycles
33 event:0x0e counters:0 um:zero minimum:500 name:FUNCTIONAL_UNIT_COMPLETION_CYCLES : Functional unit completion cycles
|
| /external/oprofile/events/mips/r12000/ |
| events | 4 event:0x0 counters:0,1,2,3 um:zero minimum:500 name:CYCLES : Cycles
|
| /external/oprofile/events/mips/rm7000/ |
| events | 4 event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Clock cycles
13 event:0x09 counters:0,1 um:zero minimum:500 name:STALL_CYCLES : Stall cycles
25 event:0x15 counters:0,1 um:zero minimum:500 name:DCACHE_MISS_STALL_CYCLES : Dcache miss stall cycles (cycles where both cache miss tokens taken and a third try is requested)
27 event:0x17 counters:0,1 um:zero minimum:500 name:FP_EXCEPTION_STALL_CYCLES : FP possible exception cycles
28 event:0x18 counters:0,1 um:zero minimum:500 name:SLIP_CYCLES_DUE_MULTIPLIER_BUSY : Slip Cycles due to multiplier busy
29 event:0x19 counters:0,1 um:zero minimum:500 name:COP0_SLIP_CYCLES : Coprocessor 0 slip cycles
30 event:0x1a counters:0,1 um:zero minimum:500 name:SLIP_CYCLES_PENDING_NON_BLKING_LOAD : Slip cycles due to pending non-blocking loads
31 event:0x1c counters:0,1 um:zero minimum:500 name:WRITE_BUFFER_FULL_STALL_CYCLES : Write buffer full stall cycles
[all...] |
| /external/llvm/lib/MC/MCDisassembler/ |
| Disassembler.cpp | 230 Latency = std::max(Latency, WLEntry->Cycles);
|
