| /art/compiler/sea_ir/ir/ |
| instruction_tools.cc | 42 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_IS_MOVE,
45 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_IS_MOVE,
48 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_IS_MOVE,
63 DF_DA | DF_A_WIDE,
78 DF_UA | DF_A_WIDE,
96 DF_DA | DF_A_WIDE | DF_SETS_CONST,
99 DF_DA | DF_A_WIDE | DF_SETS_CONST,
102 DF_DA | DF_A_WIDE | DF_SETS_CONST,
105 DF_DA | DF_A_WIDE | DF_SETS_CONST,
237 DF_DA | DF_A_WIDE | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_B | DF_CORE_C
[all...] |
| instruction_tools.h | 32 #define DF_A_WIDE (1 << kAWide)
|
| /art/compiler/dex/ |
| mir_dataflow.cc | 46 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_IS_MOVE,
49 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_IS_MOVE,
52 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_IS_MOVE,
67 DF_DA | DF_A_WIDE,
82 DF_UA | DF_A_WIDE,
100 DF_DA | DF_A_WIDE | DF_SETS_CONST,
103 DF_DA | DF_A_WIDE | DF_SETS_CONST,
106 DF_DA | DF_A_WIDE | DF_SETS_CONST,
109 DF_DA | DF_A_WIDE | DF_SETS_CONST,
241 DF_DA | DF_A_WIDE | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_B | DF_CORE_C | DF_LVN
[all...] |
| vreg_analysis.cc | 149 if (attrs & DF_A_WIDE) {
168 if (attrs & DF_A_WIDE) {
349 bool is_wide = rl_temp.wide || ((attrs & DF_A_WIDE) != 0);
377 if (attrs & DF_A_WIDE) {
388 if (attrs & DF_A_WIDE) {
|
| mir_optimization.cc | 97 if (df_attributes & DF_A_WIDE) {
[all...] |
| mir_graph.h | 116 #define DF_A_WIDE (UINT64_C(1) << kAWide)
[all...] |
| mir_graph.cc | 740 def_count_ += (df_flags & DF_A_WIDE) ? 2 : 1;
[all...] |
| /art/compiler/dex/quick/ |
| mir_to_lir.cc | 406 if (attrs & DF_A_WIDE) {
431 if (attrs & DF_A_WIDE) {
[all...] |
| /art/compiler/dex/portable/ |
| mir_to_gbc.cc | 728 if (attrs & DF_A_WIDE) {
753 if (attrs & DF_A_WIDE) {
[all...] |
| /art/compiler/dex/quick/x86/ |
| utility_x86.cc | [all...] |
