/external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
SystemZMCCodeEmitter.cpp | 132 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); 133 assert(isUInt<4>(Base) && isUInt<12>(Disp)); 134 return (Base << 12) | Disp; 142 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); 143 assert(isUInt<4>(Base) && isInt<20>(Disp)); 144 return (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12); 152 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); 154 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index)); 155 return (Index << 16) | (Base << 12) | Disp; [all...] |
/external/llvm/lib/Target/MSP430/InstPrinter/ |
MSP430InstPrinter.cpp | 64 const MCOperand &Disp = MI->getOperand(OpNo+1); 77 if (Disp.isExpr()) 78 O << *Disp.getExpr(); 80 assert(Disp.isImm() && "Expected immediate in displacement field"); 81 O << Disp.getImm();
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/external/llvm/lib/Target/SystemZ/ |
SystemZISelDAGToDAG.cpp | 57 // Base + Disp + Index + (IncludesDynAlloc ? ADJDYNALLOC : 0) 59 int64_t Disp; 64 : Form(form), DR(dr), Base(), Disp(0), Index(), 90 errs() << " Disp " << Disp; 155 SDValue &Base, SDValue &Disp) const; 157 SDValue &Base, SDValue &Disp, SDValue &Index) const; 161 // Base and Disp respectively. 163 SDValue &Base, SDValue &Disp) const; 167 // base and displacement in Base and Disp respectively [all...] |
SystemZISelLowering.cpp | [all...] |
/external/llvm/lib/Target/MSP430/ |
MSP430ISelDAGToDAG.cpp | 48 int16_t Disp; 57 : BaseType(RegBase), Disp(0), GV(nullptr), CP(nullptr), 73 errs() << " Disp " << Disp << '\n'; 124 bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp); 150 AM.Disp += G->getOffset(); 155 AM.Disp += CP->getOffset(); 192 AM.Disp += Val; 235 AM.Disp += Offset; 250 SDValue &Base, SDValue &Disp) { [all...] |
MSP430AsmPrinter.cpp | 108 const MachineOperand &Disp = MI->getOperand(OpNum+1); 113 if (Disp.isImm() && !Base.getReg())
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/external/llvm/lib/Target/X86/ |
X86InstrBuilder.h | 35 /// with BP or SP and Disp being offsetted accordingly. The displacement may 50 int Disp; 55 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr), 77 MO.push_back(MachineOperand::CreateGA(GV, Disp, GVOpFlags)); 79 MO.push_back(MachineOperand::CreateImm(Disp)); 136 MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags); 138 MIB.addImm(AM.Disp);
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X86ISelDAGToDAG.cpp | 62 int32_t Disp; 73 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0), 118 dbgs() << " Disp " << Disp << '\n' 206 SDValue &Scale, SDValue &Index, SDValue &Disp, 210 SDValue &Scale, SDValue &Index, SDValue &Disp, 213 SDValue &Scale, SDValue &Index, SDValue &Disp, 216 SDValue &Scale, SDValue &Index, SDValue &Disp, 220 SDValue &Index, SDValue &Disp, 226 SDValue &Index, SDValue &Disp, [all...] |
X86CodeEmitter.cpp | 89 intptr_t Disp = 0, intptr_t PCAdj = 0, 92 void emitConstPoolAddress(unsigned CPI, unsigned Reloc, intptr_t Disp = 0, 273 intptr_t Disp /* = 0 */, 276 intptr_t RelocCST = Disp; 290 MCE.emitDWordLE(Disp); 292 MCE.emitWordLE((int32_t)Disp); 322 intptr_t Disp /* = 0 */, 333 MCE.emitDWordLE(Disp); 335 MCE.emitWordLE((int32_t)Disp); 566 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EB [all...] |
X86FastISel.cpp | 626 // Now construct the final address. Note that the Disp, Scale, 711 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue(); 713 if (isInt<32>(Disp)) { 714 AM.Disp = (uint32_t)Disp; 725 uint64_t Disp = (int32_t)AM.Disp; 736 Disp += SL->getElementOffset(cast<ConstantInt>(Op)->getZExtValue()); 746 Disp += CI->getSExtValue() * S [all...] |
/external/llvm/lib/Target/SystemZ/Disassembler/ |
SystemZDisassembler.cpp | 192 uint64_t Disp = Field & 0xfff; 195 Inst.addOperand(MCOperand::CreateImm(Disp)); 202 uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff); 205 Inst.addOperand(MCOperand::CreateImm(SignExtend64<20>(Disp))); 213 uint64_t Disp = Field & 0xfff; 216 Inst.addOperand(MCOperand::CreateImm(Disp)); 225 uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12); 228 Inst.addOperand(MCOperand::CreateImm(SignExtend64<20>(Disp))); 237 uint64_t Disp = Field & 0xfff; 240 Inst.addOperand(MCOperand::CreateImm(Disp)); [all...] |
/external/llvm/include/llvm/CodeGen/ |
MachineInstrBuilder.h | 197 const MachineInstrBuilder &addDisp(const MachineOperand &Disp, int64_t off, 199 switch (Disp.getType()) { 203 return addImm(Disp.getImm() + off); 210 return addGlobalAddress(Disp.getGlobal(), Disp.getOffset() + off, 212 return addGlobalAddress(Disp.getGlobal(), Disp.getOffset() + off, 213 Disp.getTargetFlags());
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/external/llvm/lib/Target/X86/AsmParser/ |
X86AsmParser.cpp | 662 bool ParseIntelDotOperator(const MCExpr *Disp, const MCExpr *&NewDisp); 680 CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, 943 const MCExpr *Disp = MCConstantExpr::Create(0, getContext()); 944 return X86Operand::CreateMem(/*SegReg=*/0, Disp, /*BaseReg=*/basereg, 951 const MCExpr *Disp = MCConstantExpr::Create(0, getContext()); 952 return X86Operand::CreateMem(/*SegReg=*/0, Disp, /*BaseReg=*/basereg, 979 unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, 986 if (isa<MCSymbolRefExpr>(Disp) && !Info.IsVarDecl) { [all...] |
X86AsmInstrumentation.cpp | 202 const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx); 204 X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc())); 228 const MCExpr *Disp = MCConstantExpr::Create(1, Ctx); 230 X86Operand::CreateMem(0, Disp, X86::EDX, 0, 1, SMLoc(), SMLoc())); 290 const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx); 292 X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc())); 330 const MCExpr *Disp = MCConstantExpr::Create(Offset, Ctx); 332 X86Operand::CreateMem(0, Disp, X86::RSP, 0, 1, SMLoc(), SMLoc())); 376 const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx); 378 X86Operand::CreateMem(0, Disp, X86::RAX, 0, 1, SMLoc(), SMLoc())) [all...] |
X86Operand.h | 51 const MCExpr *Disp; 105 return Mem.Disp; 444 CreateMem(const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc, unsigned Size = 0, 448 Res->Mem.Disp = Disp; 461 CreateMem(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, 474 Res->Mem.Disp = Disp;
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/external/llvm/lib/Target/X86/MCTargetDesc/ |
X86MCCodeEmitter.cpp | 62 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp); 65 Disp.isImm() && Disp.getImm() < 0x10000) 122 void EmitImmediate(const MCOperand &Disp, SMLoc Loc, 391 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp); 421 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), 465 if (Disp.isImm() && isDisp8(Disp.getImm())) { 466 if (Disp.getImm() == 0 && BaseRegNo != N86::EBP) { 473 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups) [all...] |
/external/llvm/lib/Target/SystemZ/InstPrinter/ |
SystemZInstPrinter.cpp | 21 void SystemZInstPrinter::printAddress(unsigned Base, int64_t Disp, 23 O << Disp; 148 uint64_t Disp = MI->getOperand(OpNum + 1).getImm(); 150 O << Disp << '(' << Length;
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SystemZInstPrinter.h | 34 static void printAddress(unsigned Base, int64_t Disp, unsigned Index,
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/external/llvm/lib/Target/SystemZ/AsmParser/ |
SystemZAsmParser.cpp | 86 // Base + Disp + Index, where Base and Index are LLVM registers or 0. 95 const MCExpr *Disp; 152 createMem(RegisterKind RegKind, unsigned Base, const MCExpr *Disp, 159 Op->Mem.Disp = Disp; 214 return isMem(RegKind, MemKind) && inRange(Mem.Disp, 0, 0xfff); 217 return isMem(RegKind, MemKind) && inRange(Mem.Disp, -524288, 524287); 247 addExpr(Inst, Mem.Disp); 253 addExpr(Inst, Mem.Disp); 260 addExpr(Inst, Mem.Disp); [all...] |
/external/llvm/tools/llvm-objdump/ |
COFFDump.cpp | 225 uint64_t Offset, uint32_t Disp) { 229 if (Disp > 0) 230 Out << format(" + 0x%04x", Disp); 232 Out << format("0x%04x", Disp);
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/external/llvm/lib/Target/PowerPC/Disassembler/ |
PPCDisassembler.cpp | 264 uint64_t Disp = Imm & 0xFFFF; 288 Inst.addOperand(MCOperand::CreateImm(SignExtend64<16>(Disp))); 299 uint64_t Disp = Imm & 0x3FFF; 309 Inst.addOperand(MCOperand::CreateImm(SignExtend64<16>(Disp << 2)));
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/external/llvm/lib/Target/Mips/ |
MipsConstantIslandPass.cpp | 389 unsigned Disp, bool NegativeOK); 408 MachineInstr *CPEMI, unsigned Disp, bool NegOk, 412 bool isBBInRange(MachineInstr *MI, MachineBasicBlock *BB, unsigned Disp); [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64BranchRelaxation.cpp | 86 bool isBlockInRange(MachineInstr *MI, MachineBasicBlock *BB, unsigned Disp);
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/external/llvm/lib/Target/ARM/ |
ARMConstantIslandPass.cpp | 295 MachineInstr *CPEMI, unsigned Disp, bool NegOk, 299 bool isBBInRange(MachineInstr *MI, MachineBasicBlock *BB, unsigned Disp); 319 unsigned Disp, bool NegativeOK, bool IsSoImm = false); [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCISelDAGToDAG.cpp | 125 bool SelectAddrImm(SDValue N, SDValue &Disp, 127 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, false); 159 bool SelectAddrImmX4(SDValue N, SDValue &Disp, SDValue &Base) { 160 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, true); [all...] |