| /external/llvm/lib/Target/R600/ |
| SIFixSGPRCopies.cpp | 184 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
188 DstRC == &AMDGPU::M0RegRegClass ||
193 return TRI->isSGPRClass(DstRC) && TRI->hasVGPRs(SrcRC);
262 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC;
263 DstRC = MRI.getRegClass(MI.getOperand(0).getReg());
266 if (TRI->isSGPRClass(DstRC) &&
|
| SILowerI1Copies.cpp | 111 const TargetRegisterClass *DstRC =
116 if (DstRC == &AMDGPU::VReg_1RegClass &&
129 } else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) &&
|
| SIInstrInfo.cpp | [all...] |
| /external/llvm/utils/TableGen/ |
| FastISelEmitter.cpp | 191 const CodeGenRegisterClass *DstRC = nullptr;
273 if (DstRC) {
274 if (DstRC != RC && !DstRC->hasSubClass(RC))
277 DstRC = RC;
462 const CodeGenRegisterClass *DstRC = nullptr;
470 DstRC = &Target.getRegisterClass(Op0Rec);
471 if (!DstRC)
510 DstRC))
550 DstRC,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 156 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
161 DstRC = MRI->getRegClass(VRBase);
164 DstRC = UseRC;
166 DstRC = TLI->getRegClassFor(VT);
175 VRBase = MRI->createVirtualRegister(DstRC);
329 const TargetRegisterClass *DstRC = nullptr;
331 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
332 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
333 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
[all...] |
| /external/llvm/lib/CodeGen/ |
| PeepholeOptimizer.cpp | 279 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
280 DstRC = TM->getRegisterInfo()->getSubClassWithSubReg(DstRC, SubIdx);
281 if (!DstRC)
388 MRI->constrainRegClass(DstReg, DstRC);
[all...] |
| RegisterCoalescer.cpp | 291 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
299 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
306 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
310 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
313 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
328 CrossClass = NewRC != DstRC || NewRC != SrcRC;
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
