| /external/valgrind/main/VEX/priv/ |
| host_arm64_defs.c | [all...] |
| host_arm64_defs.h | 857 /* Move a 32-bit value to/from the FPCR */
861 } FPCR;
[all...] |
| /external/chromium_org/v8/src/arm64/ |
| disasm-arm64.cc | 1163 case FPCR: form = "'Xt, fpcr"; break;
1172 case FPCR: form = "fpcr, 'Xt"; break;
[all...] |
| simulator-arm64.cc | 88 case FPCR:
400 fpcr_ = SimSystemRegister::DefaultValueFor(FPCR);
[all...] |
| constants-arm64.h | 216 /* FPCR */ \
221 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask)
384 FPCR = ((0x1 << SysO0_offset) |
[all...] |
| macro-assembler-arm64.cc | 1369 Register fpcr = temps.AcquireX(); local
[all...] |
| /external/vixl/src/a64/ |
| disasm-a64.cc | [all...] |
| simulator-a64.cc | 53 case FPCR:
98 fpcr_ = SimSystemRegister::DefaultValueFor(FPCR);
407 if (print_all || first_run || (last_fpcr.RawValue() != fpcr().RawValue())) {
414 VIXL_ASSERT(fpcr().RMode() <= (sizeof(rmode) / sizeof(rmode[0])));
418 fpcr().AHP(), fpcr().DN(), fpcr().FZ(), rmode[fpcr().RMode()],
421 last_fpcr = fpcr();
[all...] |
| constants-a64.h | 140 /* FPCR */ \
145 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask)
274 FPCR = ((0x1 << SysO0_offset) |
[all...] |
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.cpp | 403 {"fpcr", FPCR},
|
| AArch64BaseInfo.h | 772 FPCR = 0xda20, // 11 011 0100 0100 000
[all...] |
| /external/chromium_org/v8/test/cctest/ |
| test-assembler-arm64.cc | 182 __ Msr(FPCR, xzr);
[all...] |
| test-disasm-arm64.cc | [all...] |
| /external/vixl/test/ |
| test-assembler-a64.cc | [all...] |
| test-disasm-a64.cc | [all...] |
| /external/llvm/test/MC/AArch64/ |
| basic-a64-instructions.s | [all...] |
| /external/valgrind/main/memcheck/ |
| mc_machine.c | [all...] |
