/external/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 481 /// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, 485 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, [all...] |
/external/llvm/lib/CodeGen/ |
BasicTargetTransformInfo.cpp | 572 case Intrinsic::pow: ISD = ISD::FPOW; break;
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/external/llvm/lib/CodeGen/SelectionDAG/ |
SelectionDAGDumper.cpp | 190 case ISD::FPOW: return "fpow";
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LegalizeFloatTypes.cpp | 89 case ISD::FPOW: R = SoftenFloatRes_FPOW(N); break; [all...] |
LegalizeVectorOps.cpp | 281 case ISD::FPOW: [all...] |
LegalizeVectorTypes.cpp | 109 case ISD::FPOW: 633 case ISD::FPOW: [all...] |
LegalizeDAG.cpp | [all...] |
SelectionDAGBuilder.cpp | [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonISelLowering.cpp | [all...] |
/external/llvm/lib/Target/Sparc/ |
SparcISelLowering.cpp | [all...] |
/external/llvm/lib/Target/R600/ |
AMDGPUISelLowering.cpp | 126 setOperationAction(ISD::FPOW, MVT::f32, Legal); 341 setOperationAction(ISD::FPOW, VT, Expand); [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64ISelLowering.cpp | 167 setOperationAction(ISD::FPOW, MVT::f128, Expand); 276 setOperationAction(ISD::FPOW, MVT::f32, Expand); 277 setOperationAction(ISD::FPOW, MVT::f64, Expand); 400 setOperationAction(ISD::FPOW, MVT::v1f64, Expand); 501 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand); [all...] |
/external/llvm/lib/Target/Mips/ |
MipsISelLowering.cpp | 333 setOperationAction(ISD::FPOW, MVT::f32, Expand); 334 setOperationAction(ISD::FPOW, MVT::f64, Expand); [all...] |
/external/llvm/lib/Target/ARM/ |
ARMISelLowering.cpp | 463 setOperationAction(ISD::FPOW, MVT::v2f64, Expand); 481 setOperationAction(ISD::FPOW, MVT::v4f32, Expand); 498 setOperationAction(ISD::FPOW, MVT::v2f32, Expand); [all...] |
/external/llvm/lib/Target/X86/ |
X86ISelLowering.cpp | [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCISelLowering.cpp | 166 setOperationAction(ISD::FPOW , MVT::f64, Expand); 172 setOperationAction(ISD::FPOW , MVT::f32, Expand); 461 setOperationAction(ISD::FPOW, VT, Expand); [all...] |