| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 418 /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type
421 /// normal rounding, if it is 1, this FP_ROUND is known to not change the
427 /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for
428 /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed.
429 FP_ROUND,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorTypes.cpp | 56 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
192 return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
425 case ISD::FP_ROUND:
524 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
603 case ISD::FP_ROUND:
[all...] |
| LegalizeFloatTypes.cpp | 87 case ISD::FP_ROUND: R = SoftenFloatRes_FP_ROUND(N); break;
394 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
628 case ISD::FP_ROUND: Res = SoftenFloatOp_FP_ROUND(N); break;
662 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND libcall");
[all...] |
| SelectionDAGDumper.cpp | 228 case ISD::FP_ROUND: return "fp_round";
|
| LegalizeDAG.cpp | [all...] |
| DAGCombiner.cpp | 503 case ISD::FP_ROUND:
582 case ISD::FP_ROUND:
583 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(),
[all...] |
| LegalizeVectorOps.cpp | 293 case ISD::FP_ROUND:
[all...] |
| SelectionDAG.cpp | [all...] |
| SelectionDAGBuilder.cpp | 204 // FP_ROUND's are always exact here.
206 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 191 { ISD::FP_ROUND, MVT::v2f64, 2 },
196 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND ||
|
| ARMISelLowering.cpp | 532 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 195 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
196 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
419 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 150 setTargetDAGCombine(ISD::FP_ROUND);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 500 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
532 if (N->getOpcode() == ISD::FP_ROUND)
533 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
549 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 134 // from FP_ROUND: that rounds to nearest, this rounds to zero.
[all...] |
