| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 342 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 },
343 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
344 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 },
350 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 2 },
351 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 1 },
352 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 1 },
357 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
358 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 2 },
364 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 },
365 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 }
[all...] |
| AArch64ISelLowering.cpp | 186 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
187 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
188 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
416 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
538 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 264 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
266 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 },
268 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
282 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 },
284 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 4 },
286 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 }
300 { ISD::FP_TO_UINT, MVT::i1, MVT::f32, 2 },
302 { ISD::FP_TO_UINT, MVT::i1, MVT::f64, 2 },
304 { ISD::FP_TO_UINT, MVT::i8, MVT::f32, 2 },
306 { ISD::FP_TO_UINT, MVT::i8, MVT::f64, 2 }
[all...] |
| ARMISelLowering.cpp | 108 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
113 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
529 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
564 setTargetDAGCombine(ISD::FP_TO_UINT);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 416 FP_TO_UINT,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 273 case ISD::FP_TO_UINT:
350 case ISD::FP_TO_UINT:
428 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) {
429 NewOpc = ISD::FP_TO_UINT;
[all...] |
| SelectionDAGDumper.cpp | 236 case ISD::FP_TO_UINT: return "fp_to_uint";
|
| LegalizeVectorTypes.cpp | 89 case ISD::FP_TO_UINT:
605 case ISD::FP_TO_UINT:
[all...] |
| LegalizeIntegerTypes.cpp | 100 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
386 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
390 if (N->getOpcode() == ISD::FP_TO_UINT &&
391 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
400 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
[all...] |
| LegalizeFloatTypes.cpp | 630 case ISD::FP_TO_UINT: Res = SoftenFloatOp_FP_TO_UINT(N); break;
[all...] |
| LegalizeDAG.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 661 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 },
662 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 },
[all...] |
| X86ISelLowering.cpp | 384 // Handle FP_TO_UINT by promoting the destination to a larger signed
386 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
387 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
388 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
391 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
396 // Expand FP_TO_UINT into a select.
399 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
409 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom)
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 277 setOperationAction(ISD::FP_TO_UINT, Ty, Legal);
[all...] |
| MipsISelLowering.cpp | 299 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
300 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 355 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
365 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
366 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
373 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
379 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
493 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
602 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 84 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
842 case ISD::FP_TO_UINT: Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG));
[all...] |
| AMDGPUISelLowering.cpp | 292 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 181 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
[all...] |
