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    Searched refs:GPR4AlignEncode (Results 1 - 6 of 6) sorted by null

/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
AMDGPUCodeEmitter.h	24 virtual unsigned GPR4AlignEncode(const MachineInstr &MI,
/external/mesa3d/src/gallium/drivers/radeon/
AMDGPUCodeEmitter.h	24 virtual unsigned GPR4AlignEncode(const MachineInstr &MI,
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/
AMDGPUMCCodeEmitter.h	36 virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo,
SIMCCodeEmitter.cpp	90 /// GPR4AlignEncode - Encoding for when 4 consectuive registers are used 91 virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo, 173 unsigned SIMCCodeEmitter::GPR4AlignEncode(const MCInst &MI,
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
AMDGPUMCCodeEmitter.h	36 virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo,
SIMCCodeEmitter.cpp	90 /// GPR4AlignEncode - Encoding for when 4 consectuive registers are used 91 virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo, 173 unsigned SIMCCodeEmitter::GPR4AlignEncode(const MCInst &MI,

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