| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | 1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
15 #include "Hexagon.h"
32 #define DEBUG_TYPE "hexagon-instrinfo"
40 /// Constants for Hexagon instructions.
65 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
81 case Hexagon::LDriw:
82 case Hexagon::LDrid:
83 case Hexagon::LDrih
[all...] |
| HexagonRegisterInfo.cpp | 1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
16 #include "Hexagon.h"
42 : HexagonGenRegisterInfo(Hexagon::R31),
49 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
52 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19
[all...] |
| HexagonSplitTFRCondSets.cpp | 29 #include "Hexagon.h"
72 return "Hexagon Split TFRCondSets";
95 case Hexagon::TFR_condset_rr:
96 case Hexagon::TFR_condset_rr_f:
97 case Hexagon::TFR_condset_rr64_f: {
102 if (MI->getOpcode() == Hexagon::TFR_condset_rr ||
103 MI->getOpcode() == Hexagon::TFR_condset_rr_f) {
104 Opc1 = Hexagon::TFR_cPt;
105 Opc2 = Hexagon::TFR_cNotPt;
107 else if (MI->getOpcode() == Hexagon::TFR_condset_rr64_f)
[all...] |
| HexagonSplitConst32AndConst64.cpp | 59 return "Hexagon Split Const32s and Const64s";
88 if (Opc == Hexagon::CONST32_set) {
93 TII->get(Hexagon::LO), DestReg).addOperand(Symbol);
95 TII->get(Hexagon::HI), DestReg).addOperand(Symbol);
101 else if (Opc == Hexagon::CONST32_set_jt) {
106 TII->get(Hexagon::LO_jt), DestReg).addOperand(Symbol);
108 TII->get(Hexagon::HI_jt), DestReg).addOperand(Symbol);
114 else if (Opc == Hexagon::CONST32_Label) {
119 TII->get(Hexagon::LO_label), DestReg).addOperand(Symbol);
121 TII->get(Hexagon::HI_label), DestReg).addOperand(Symbol)
[all...] |
| HexagonVarargsCallingConvention.h | 53 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
54 Hexagon::R5
66 Hexagon::D0, Hexagon::D1, Hexagon::D2
109 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4
[all...] |
| HexagonNewValueJump.cpp | 1 //===----- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -------===//
10 // This implements NewValueJump pass in Hexagon.
25 #include "Hexagon.h"
49 #define DEBUG_TYPE "hexagon-nvj"
84 return "Hexagon NewValueJump";
99 INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj",
100 "Hexagon NewValueJump", false, false)
102 INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj",
103 "Hexagon NewValueJump", false, false)
179 if (MII->getOpcode() == Hexagon::CALLv3
[all...] |
| HexagonExpandPredSpillCode.cpp | 9 // The Hexagon processor has no instructions that load or store predicate
20 #include "Hexagon.h"
64 return "Hexagon Expand Predicate Spill Code";
86 if (Opc == Hexagon::STriw_pred) {
94 assert(Hexagon::PredRegsRegClass.contains(SrcReg) &&
96 if (!TII->isValidOffset(Hexagon::STriw_indexed, Offset)) {
97 if (!TII->isValidOffset(Hexagon::ADD_ri, Offset)) {
99 TII->get(Hexagon::CONST32_Int_Real),
101 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr),
104 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd)
[all...] |
| HexagonCFGOptimizer.cpp | 9 #include "Hexagon.h"
53 return "Hexagon CFG Optimizer";
62 return (Opc == Hexagon::JMP_t) || (Opc == Hexagon::JMP_f)
63 || (Opc == Hexagon::JMP_tnew_t) || (Opc == Hexagon::JMP_fnew_t);
68 return (Opc == Hexagon::JMP);
78 case Hexagon::JMP_t:
79 NewOpcode = Hexagon::JMP_f;
82 case Hexagon::JMP_f
[all...] |
| HexagonMachineFunctionInfo.h | 1 //=- HexagonMachineFunctionInfo.h - Hexagon machine function info -*- C++ -*-=//
18 namespace Hexagon {
24 /// Hexagon target-specific information for each MachineFunction.
59 PacketInfo[MI] |= Hexagon::StartPacket;
62 PacketInfo[MI] |= Hexagon::EndPacket;
66 (PacketInfo.find(MI)->second & Hexagon::StartPacket));
70 (PacketInfo.find(MI)->second & Hexagon::EndPacket));
|
| HexagonFixupHwLoops.cpp | 18 #include "Hexagon.h"
46 return "Hexagon Hardware Loop Fixup";
75 "Hexagon Hardware Loops Fixup", false, false)
84 return MI->getOpcode() == Hexagon::LOOP0_r ||
85 MI->getOpcode() == Hexagon::LOOP0_i;
95 /// \brief For Hexagon, if the loop label is to far from the
166 unsigned Scratch = RS.scavengeRegister(&Hexagon::IntRegsRegClass, MII, 0);
171 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::LC0)
175 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFRI), Scratch
[all...] |
| Makefile | 1 ##===- lib/Target/Hexagon/Makefile -------------------------*- Makefile -*-===##
11 TARGET = Hexagon
|
| HexagonFrameLowering.cpp | 12 #include "Hexagon.h"
40 "disable-hexagon-dealloc-ret",
42 cl::desc("Disable Dealloc Return for Hexagon target"));
103 assert((MI->getOpcode() == Hexagon::ADJDYNALLOC) &&
122 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(0);
125 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::CONST32_Int_Real),
127 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::SUB_rr),
132 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(NumBytes);
142 return RetOpcode == Hexagon::TCRETURNtg || RetOpcode == Hexagon::TCRETURNtext
[all...] |
| HexagonPeephole.cpp | 1 //===-- HexagonPeephole.cpp - Hexagon Peephole Optimiztions ---------------===//
38 #include "Hexagon.h"
59 #define DEBUG_TYPE "hexagon-peephole"
61 static cl::opt<bool> DisableHexagonPeephole("disable-hexagon-peephole",
65 static cl::opt<bool> DisablePNotP("disable-hexagon-pnotp",
69 static cl::opt<bool> DisableOptSZExt("disable-hexagon-optszext",
73 static cl::opt<bool> DisableOptExtTo64("disable-hexagon-opt-ext-to-64",
96 return "Hexagon optimize redundant zero and size extends";
110 INITIALIZE_PASS(HexagonPeephole, "hexagon-peephole", "Hexagon Peephole"
[all...] |
| HexagonCopyToCombine.cpp | 1 //===------- HexagonCopyToCombine.cpp - Hexagon Copy-To-Combine Pass ------===//
15 #include "Hexagon.h"
37 #define DEBUG_TYPE "hexagon-copy-combine"
76 return "Hexagon Copy-To-Combine Pass";
110 INITIALIZE_PASS(HexagonCopyToCombine, "hexagon-copy-combine",
111 "Hexagon Copy-To-Combine Pass", false, false)
117 case Hexagon::TFR: {
123 return Hexagon::IntRegsRegClass.contains(DestReg) &&
124 Hexagon::IntRegsRegClass.contains(SrcReg);
127 case Hexagon::TFRI:
[all...] |
| HexagonRegisterInfo.h | 1 //==- HexagonRegisterInfo.h - Hexagon Register Information Impl --*- C++ -*-==//
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
36 #define HEXAGON_RESERVED_REG_1 Hexagon::R10
37 #define HEXAGON_RESERVED_REG_2 Hexagon::R11
|
| HexagonISelDAGToDAG.cpp | 1 //===-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon --===//
10 // This file defines an instruction selector for the Hexagon target.
14 #include "Hexagon.h"
25 #define DEBUG_TYPE "hexagon-isel"
43 /// HexagonDAGToDAGISel - Hexagon specific code to select Hexagon machine
48 /// Subtarget - Keep a pointer to the Hexagon Subtarget around so that we can
83 return "Hexagon DAG->DAG Pattern Instruction Selection";
180 /// Hexagon-specific DAG, ready for instruction scheduling.
188 const char *Name = "Hexagon DAG->DAG Pattern Instruction Selection"
[all...] |
| HexagonHardwareLoops.cpp | 10 // This pass identifies loops where we can generate the Hexagon hardware
30 #include "Hexagon.h"
83 const char *getPassName() const override { return "Hexagon Hardware Loops"; }
278 "Hexagon Hardware Loops", false, false)
282 "Hexagon Hardware Loops", false, false)
287 return MI->getOpcode() == Hexagon::LOOP0_r ||
288 MI->getOpcode() == Hexagon::LOOP0_i;
297 DEBUG(dbgs() << "********* Hexagon Hardware Loops *********\n");
357 bool isAdd = (UpdOpc == Hexagon::ADD_ri);
540 case Hexagon::CMPEQri
[all...] |
| HexagonVLIWPacketizer.cpp | 20 #include "Hexagon.h"
55 static cl::opt<bool> PacketizeVolatiles("hexagon-packetize-volatiles",
84 return "Hexagon Packetizer";
175 INITIALIZE_PASS_BEGIN(HexagonPacketizer, "packets", "Hexagon Packetizer",
181 INITIALIZE_PASS_END(HexagonPacketizer, "packets", "Hexagon Packetizer",
269 return ((MI->getOpcode() == Hexagon::CALLR) ||
270 (MI->getOpcode() == Hexagon::CALLRv3));
278 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
296 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
308 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i)
[all...] |
| HexagonISelLowering.cpp | 1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
10 // This file implements the interfaces that Hexagon uses to lower LLVM code
42 #define DEBUG_TYPE "hexagon-lowering"
45 EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden,
46 cl::desc("Control jump table emission on Hexagon target"));
63 // Implement calling convention for Hexagon.
188 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4
[all...] |
| HexagonCallingConvLower.cpp | 17 #include "Hexagon.h"
98 // For Hexagon, Return small structures in registers.
101 unsigned Reg = Hexagon::R0;
107 unsigned Reg = Hexagon::D0;
|
| HexagonAsmPrinter.cpp | 1 //===-- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly --===//
11 // of machine-dependent LLVM code to Hexagon assembly language. This printer is
16 #include "Hexagon.h"
61 "hexagon-align-calls", cl::Hidden, cl::init(true),
62 cl::desc("Insert falign after call instruction for Hexagon target"));
122 // Hexagon never has a prefix.
172 /// printMachineInstruction -- Print out a single Hexagon MI in Darwin syntax to
208 if (MI->getOpcode() == Hexagon::ENDLOOP0) {
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCTargetDesc.cpp | 1 //===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
10 // This file provides Hexagon specific target descriptions.
45 InitHexagonMCRegisterInfo(X, Hexagon::R0);
63 nullptr, Hexagon::R30, 0);
|
| /external/clang/include/clang/Basic/ |
| TargetBuiltins.h | 138 /// \brief Hexagon builtins
139 namespace Hexagon {
|
| /external/llvm/lib/Target/Hexagon/InstPrinter/ |
| HexagonInstPrinter.cpp | 1 //===- HexagonInstPrinter.cpp - Convert Hexagon MCInst to assembly syntax -===//
10 // This class prints an Hexagon MCInst to a .s file.
15 #include "Hexagon.h"
51 if (MI->getOpcode() == Hexagon::ENDLOOP0) {
61 Nop.setOpcode (Hexagon::NOP);
|
| /external/clang/lib/Basic/ |
| Targets.cpp | [all...] |
