| /external/llvm/include/llvm/Target/ |
| TargetOpcodes.h | 43 /// INSERT_SUBREG - This instruction takes three operands: a register that
49 INSERT_SUBREG = 7,
54 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
|
| /external/llvm/lib/CodeGen/ |
| ExpandPostRAPseudos.cpp | 91 assert(SubIdx != 0 && "Invalid index for insert_subreg");
218 case TargetOpcode::INSERT_SUBREG:
|
| /external/llvm/lib/Target/R600/ |
| SIFixSGPRCopies.cpp | 261 case AMDGPU::INSERT_SUBREG: {
268 DEBUG(dbgs() << " Fixing INSERT_SUBREG:\n");
|
| R600OptimizeVectorRegisters.cpp | 23 /// vreg7<def> = INSERT_SUBREG vreg4, sub3
195 MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::INSERT_SUBREG),
|
| SIInstrInfo.cpp | 684 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
751 case AMDGPU::INSERT_SUBREG:
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 712 return getOpcode() == TargetOpcode::INSERT_SUBREG;
755 case TargetOpcode::INSERT_SUBREG:
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ResourcePriorityQueue.cpp | 266 case TargetOpcode::INSERT_SUBREG:
306 case TargetOpcode::INSERT_SUBREG:
|
| InstrEmitter.cpp | 521 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
531 // the INSERT_SUBREG instruction.
533 // %dst = INSERT_SUBREG %src, %sub, SubIdx
544 assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
549 // Create the insert_subreg or subreg_to_reg machine instruction.
567 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
714 Opc == TargetOpcode::INSERT_SUBREG ||
[all...] |
| ScheduleDAGRRList.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonMachineScheduler.cpp | 54 case TargetOpcode::INSERT_SUBREG:
106 case TargetOpcode::INSERT_SUBREG:
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 238 // If the use is an INSERT_SUBREG, that's still something that can
241 // vector is an IMPLICIT_DEF, the INSERT_SUBREG just goes away entirely.
243 else if (Use->getOpcode() == AArch64::INSERT_SUBREG ||
|
| AArch64ISelDAGToDAG.cpp | 670 TargetOpcode::INSERT_SUBREG, SDLoc(N), MVT::i64, ImpDef, N, SubReg);
[all...] |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 261 // See if the first operand of this insert_subreg is IMPLICIT_DEF
331 // INSERT_SUBREG or REG_SEQUENCE.
504 TII->get(TargetOpcode::INSERT_SUBREG), Out)
585 // D/Q registers. These can only be caused by COPY, INSERT_SUBREG and
601 // * INSERT_SUBREG: * If the SPR value was originally in another DPR/QPR
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | [all...] |
