| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AddressingModes.h | 73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) {
74 switch ((Imm >> 6) & 0x7) {
85 static inline unsigned getShiftValue(unsigned Imm) {
86 return Imm & 0x3f;
90 /// imm: 6-bit shift amount
97 /// {5-0} = imm
99 unsigned Imm) {
100 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!");
110 return (STEnc << 6) | (Imm & 0x3f)
[all...] |
| /external/llvm/lib/Target/X86/Utils/ |
| X86ShuffleDecode.h | 31 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
39 void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
41 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
43 void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
45 void DecodePSHUFLWMask(MVT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
50 void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
63 void DecodeVPERM2X128Mask(MVT VT, unsigned Imm,
68 void DecodeVPERMMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
|
| X86ShuffleDecode.cpp | 24 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
32 unsigned ZMask = Imm & 15;
33 unsigned CountD = (Imm >> 4) & 3;
34 unsigned CountS = (Imm >> 6) & 3;
65 void DecodePALIGNRMask(MVT VT, unsigned Imm,
68 unsigned Offset = Imm * (VT.getVectorElementType().getSizeInBits() / 8);
86 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
92 unsigned NewImm = Imm;
98 if (NumLaneElts == 4) NewImm = Imm; // reload imm
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAddressingModes.h | 106 // reg [asr|lsl|lsr|ror|rrx] imm
109 // reg, the second is the shift amount (or reg0 if not present or imm). The
110 // third operand encodes the shift opcode and the imm if a reg isn't present.
112 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
113 return ShOp | (Imm << 3);
122 /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
123 /// the 8-bit imm value.
124 static inline unsigned getSOImmValImm(unsigned Imm) {
125 return Imm & 0xFF
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsAnalyzeImmediate.cpp | 29 void MipsAnalyzeImmediate::GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize,
31 GetInstSeqLs((Imm + 0x8000ULL) & 0xffffffffffff0000ULL, RemSize, SeqLs);
32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL));
35 void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize,
37 GetInstSeqLs(Imm & 0xffffffffffff0000ULL, RemSize, SeqLs);
38 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL));
41 void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize,
43 unsigned Shamt = countTrailingZeros(Imm);
44 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs);
48 void MipsAnalyzeImmediate::GetInstSeqLs(uint64_t Imm, unsigned RemSize
[all...] |
| MipsISelDAGToDAG.h | 56 /// (reg + imm).
84 virtual bool selectVSplat(SDNode *N, APInt &Imm) const;
86 virtual bool selectVSplatUimm1(SDValue N, SDValue &Imm) const;
88 virtual bool selectVSplatUimm2(SDValue N, SDValue &Imm) const;
90 virtual bool selectVSplatUimm3(SDValue N, SDValue &Imm) const;
92 virtual bool selectVSplatUimm4(SDValue N, SDValue &Imm) const;
94 virtual bool selectVSplatUimm5(SDValue N, SDValue &Imm) const;
96 virtual bool selectVSplatUimm6(SDValue N, SDValue &Imm) const;
98 virtual bool selectVSplatUimm8(SDValue N, SDValue &Imm) const;
100 virtual bool selectVSplatSimm5(SDValue N, SDValue &Imm) const
[all...] |
| MipsAnalyzeImmediate.h | 25 /// Analyze - Get an instruction sequence to load immediate Imm. The last
28 const InstSeq &Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu);
36 /// load immediate Imm
37 void GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
40 /// load immediate Imm
41 void GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
44 /// load immediate Imm
45 void GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
47 /// GetInstSeqLs - Get instruction sequences to load immediate Imm.
48 void GetInstSeqLs(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs)
[all...] |
| MipsSEISelDAGToDAG.h | 72 bool selectVSplat(SDNode *N, APInt &Imm) const override;
74 bool selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
77 bool selectVSplatUimm1(SDValue N, SDValue &Imm) const override;
79 bool selectVSplatUimm2(SDValue N, SDValue &Imm) const override;
81 bool selectVSplatUimm3(SDValue N, SDValue &Imm) const override;
83 bool selectVSplatUimm4(SDValue N, SDValue &Imm) const override;
85 bool selectVSplatUimm5(SDValue N, SDValue &Imm) const override;
87 bool selectVSplatUimm6(SDValue N, SDValue &Imm) const override;
89 bool selectVSplatUimm8(SDValue N, SDValue &Imm) const override;
91 bool selectVSplatSimm5(SDValue N, SDValue &Imm) const override
[all...] |
| MipsISelDAGToDAG.cpp | 110 bool MipsDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const {
115 bool MipsDAGToDAGISel::selectVSplatUimm1(SDValue N, SDValue &Imm) const {
120 bool MipsDAGToDAGISel::selectVSplatUimm2(SDValue N, SDValue &Imm) const {
125 bool MipsDAGToDAGISel::selectVSplatUimm3(SDValue N, SDValue &Imm) const {
130 bool MipsDAGToDAGISel::selectVSplatUimm4(SDValue N, SDValue &Imm) const {
135 bool MipsDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &Imm) const {
140 bool MipsDAGToDAGISel::selectVSplatUimm6(SDValue N, SDValue &Imm) const {
145 bool MipsDAGToDAGISel::selectVSplatUimm8(SDValue N, SDValue &Imm) const {
150 bool MipsDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &Imm) const {
155 bool MipsDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const
[all...] |
| MipsFastISel.cpp | 86 unsigned Materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
323 int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
327 unsigned TempReg = Materialize32BitInt(Imm, &Mips::GPR32RegClass);
333 unsigned TempReg1 = Materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
335 Materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
362 int64_t Imm;
364 Imm = CI->getSExtValue();
366 Imm = CI->getZExtValue();
367 return Materialize32BitInt(Imm, RC);
370 unsigned MipsFastISel::Materialize32BitInt(int64_t Imm,
[all...] |
| MipsSEISelDAGToDAG.cpp | 407 // Returns true and sets Imm if:
410 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const {
428 Imm = SplatValue;
436 // true and sets Imm if:
450 selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
462 Imm = CurDAG->getTargetConstant(ImmValue, EltTy);
472 selectVSplatUimm1(SDValue N, SDValue &Imm) const {
473 return selectVSplatCommon(N, Imm, false, 1);
477 selectVSplatUimm2(SDValue N, SDValue &Imm) const {
478 return selectVSplatCommon(N, Imm, false, 2)
[all...] |
| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 88 IntFloatUnion Imm;
90 Imm.I = MO.getImm();
92 Imm.F = MO.getFPImm();
96 if (Imm.I >= 0 && Imm.I <= 64)
97 return 128 + Imm.I;
99 if (Imm.I >= -16 && Imm.I <= -1)
100 return 192 + abs(Imm.I);
102 if (Imm.F == 0.5f
[all...] |
| /external/llvm/lib/MC/ |
| MCInstrAnalysis.cpp | 19 int64_t Imm = Inst.getOperand(0).getImm();
20 Target = Addr+Size+Imm;
|
| /external/llvm/test/MC/Mips/ |
| sym-expr.s | 11 jal __start + 0x4 # CHECK: instruction: [jal, Imm<__start+4>]
12 jal __start + (-0x10) # CHECK: instruction: [jal, Imm<__start-16>]
13 jal (__start + (-0x10)) # CHECK: instruction: [jal, Imm<__start-16>]
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCTargetTransformInfo.cpp | 75 unsigned getIntImmCost(const APInt &Imm, Type *Ty) const override;
77 unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
79 unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
138 unsigned PPCTTI::getIntImmCost(const APInt &Imm, Type *Ty) const {
140 return TargetTransformInfo::getIntImmCost(Imm, Ty);
148 if (Imm == 0)
151 if (Imm.getBitWidth() <= 64) {
152 if (isInt<16>(Imm.getSExtValue()))
155 if (isInt<32>(Imm.getSExtValue())) {
157 if ((Imm.getZExtValue() & 0xFFFF) == 0
[all...] |
| PPCISelDAGToDAG.cpp | 82 inline SDValue getI32Imm(unsigned Imm) {
83 return CurDAG->getTargetConstant(Imm, MVT::i32);
88 inline SDValue getI64Imm(uint64_t Imm) {
89 return CurDAG->getTargetConstant(Imm, MVT::i64);
93 inline SDValue getSmallIPtrImm(unsigned Imm) {
94 return CurDAG->getTargetConstant(Imm, PPCLowering->getPointerTy());
124 /// a base register plus a signed 16-bit displacement [r+imm].
145 /// be represented by [r+imm], which are preferred.
295 static bool isIntS16Immediate(SDNode *N, short &Imm) {
299 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue()
[all...] |
| /external/llvm/lib/Target/SystemZ/Disassembler/ |
| SystemZDisassembler.cpp | 110 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) {
111 assert(isUInt<N>(Imm) && "Invalid immediate");
112 Inst.addOperand(MCOperand::CreateImm(Imm));
117 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) {
118 assert(isUInt<N>(Imm) && "Invalid immediate");
119 Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm)));
123 static DecodeStatus decodeAccessRegOperand(MCInst &Inst, uint64_t Imm,
126 return decodeUImmOperand<4>(Inst, Imm);
129 static DecodeStatus decodeU4ImmOperand(MCInst &Inst, uint64_t Imm,
131 return decodeUImmOperand<4>(Inst, Imm);
[all...] |
| /external/llvm/lib/Target/NVPTX/InstPrinter/ |
| NVPTXInstPrinter.cpp | 89 O << markup("<imm:") << formatImm(Op.getImm()) << markup(">");
99 int64_t Imm = MO.getImm();
103 if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG)
107 if (Imm & NVPTX::PTXCvtMode::SAT_FLAG)
111 switch (Imm & NVPTX::PTXCvtMode::BASE_MASK) {
149 int64_t Imm = MO.getImm();
153 if (Imm & NVPTX::PTXCmpMode::FTZ_FLAG)
156 switch (Imm & NVPTX::PTXCmpMode::BASE_MASK) {
223 int Imm = (int) MO.getImm();
225 if (Imm)
[all...] |
| /external/llvm/lib/Target/R600/InstPrinter/ |
| AMDGPUInstPrinter.cpp | 113 void AMDGPUInstPrinter::printImmediate(uint32_t Imm, raw_ostream &O) {
114 int32_t SImm = static_cast<int32_t>(Imm);
120 if (Imm == FloatToBits(1.0f) ||
121 Imm == FloatToBits(-1.0f) ||
122 Imm == FloatToBits(0.5f) ||
123 Imm == FloatToBits(-0.5f) ||
124 Imm == FloatToBits(2.0f) ||
125 Imm == FloatToBits(-2.0f) ||
126 Imm == FloatToBits(4.0f) ||
127 Imm == FloatToBits(-4.0f))
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIInstrInfo.h | 46 int64_t Imm) const;
|
| SIInstrInfo.cpp | 53 int64_t Imm) const
57 MachineInstrBuilder(MI).addImm(Imm);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIInstrInfo.h | 46 int64_t Imm) const;
|
| SIInstrInfo.cpp | 53 int64_t Imm) const
57 MachineInstrBuilder(MI).addImm(Imm);
|
| /external/llvm/include/llvm/Analysis/ |
| TargetTransformInfo.h | 254 virtual bool isLegalAddImmediate(int64_t Imm) const;
260 virtual bool isLegalICmpImmediate(int64_t Imm) const;
307 virtual unsigned getIntImmCost(const APInt &Imm, Type *Ty) const;
312 virtual unsigned getIntImmCost(unsigned Opc, unsigned Idx, const APInt &Imm,
315 const APInt &Imm, Type *Ty) const;
|
| /external/llvm/include/llvm/CodeGen/ |
| FastISel.h | 210 uint64_t Imm);
229 uint64_t Imm);
239 uint64_t Imm, MVT ImmType);
246 uint64_t Imm);
287 uint64_t Imm);
308 uint64_t Imm);
322 uint64_t Imm);
|
