| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 49 unsigned IndexReg;
55 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr),
73 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false,
134 MIB.addImm(AM.Scale).addReg(AM.IndexReg);
|
| X86AsmPrinter.cpp | 236 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
246 bool HasParenPart = IndexReg.getReg() || HasBaseReg;
266 assert(IndexReg.getReg() != X86::ESP &&
273 if (IndexReg.getReg()) {
302 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
320 if (IndexReg.getReg()) {
333 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
|
| X86CodeEmitter.cpp | 480 const MachineOperand &IndexReg = MI.getOperand(Op+2);
487 assert(IndexReg.getReg() == 0 && Is64BitMode &&
508 IndexReg.getReg() == 0 &&
546 assert(IndexReg.getReg() != X86::ESP &&
547 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
580 if (IndexReg.getReg())
581 IndexRegNo = getX86RegNum(IndexReg.getReg());
588 if (IndexReg.getReg())
589 IndexRegNo = getX86RegNum(IndexReg.getReg());
614 const MachineOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg)
[all...] |
| X86ISelDAGToDAG.cpp | 61 SDValue IndexReg;
73 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
85 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr;
113 << "IndexReg ";
114 if (IndexReg.getNode())
115 IndexReg.getNode()->dump();
245 Index = AM.IndexReg;
745 AM.Base_Reg = AM.IndexReg;
757 AM.IndexReg.getNode() == nullptr &&
816 AM.IndexReg = And
[all...] |
| X86MCInstLower.cpp | 691 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
692 Opc = IndexReg = Displacement = SegmentReg = 0;
701 IndexReg = X86::RAX; break;
703 IndexReg = X86::RAX; break;
706 IndexReg = X86::RAX; break;
708 IndexReg = X86::RAX; break;
710 IndexReg = X86::RAX; SegmentReg = X86::CS; break;
729 .addReg(IndexReg)
[all...] |
| X86FastISel.cpp | 559 (AM.Base.Reg == 0 && AM.IndexReg == 0)) {
578 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
640 if (AM.IndexReg == 0) {
642 AM.IndexReg = getRegForValue(V);
643 return AM.IndexReg != 0;
726 unsigned IndexReg = AM.IndexReg;
758 if (IndexReg == 0 &&
763 IndexReg = getRegForGEPIndex(Op).first;
764 if (IndexReg == 0
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 253 unsigned BaseReg, IndexReg, TmpReg, Scale;
262 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
267 unsigned getIndexReg() { return IndexReg; }
355 // If we already have a BaseReg, then assume this is the IndexReg with
360 assert (!IndexReg && "BaseReg/IndexReg already set!");
361 IndexReg = TmpReg;
392 // If we already have a BaseReg, then assume this is the IndexReg with
397 assert (!IndexReg && "BaseReg/IndexReg already set!")
[all...] |
| X86Operand.h | 53 unsigned IndexReg;
117 return Mem.IndexReg;
450 Res->Mem.IndexReg = 0;
462 unsigned IndexReg, unsigned Scale, SMLoc StartLoc, SMLoc EndLoc,
467 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
476 Res->Mem.IndexReg = IndexReg;
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86ATTInstPrinter.cpp | 187 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
201 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
208 if (IndexReg.getReg() || BaseReg.getReg()) {
213 if (IndexReg.getReg()) {
|
| X86IntelInstPrinter.cpp | 168 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
186 if (IndexReg.getReg()) {
200 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 61 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
69 (IndexReg.getReg() != 0 &&
70 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
250 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
254 (IndexReg.getReg() != 0 &&
255 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
265 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
269 (IndexReg.getReg() != 0 &&
270 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg())))
394 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg)
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIInstrInfo.h | 175 unsigned SavReg, unsigned IndexReg) const;
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 151 unsigned &IndexReg);
397 unsigned &IndexReg) {
419 IndexReg = PPCMaterializeInt(Offset, MVT::i64);
420 assert(IndexReg && "Unexpected error in PPCMaterializeInt!");
484 unsigned IndexReg = 0;
485 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
531 .addReg(Addr.Base.Reg).addReg(IndexReg);
603 unsigned IndexReg = 0;
604 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
645 .addReg(SrcReg).addReg(Addr.Base.Reg).addReg(IndexReg);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | [all...] |
