/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
HexagonMCInst.h | 24 // MCID is set during instruction lowering. 27 const MCInstrDesc *MCID; 34 MCInst(), MCID(nullptr), packetStart(0), packetEnd(0) {}; 35 HexagonMCInst(const MCInstrDesc& mcid): 36 MCInst(), MCID(&mcid), packetStart(0), packetEnd(0) {}; 50 void setDesc(const MCInstrDesc& mcid) { MCID = &mcid; }; 51 const MCInstrDesc& getDesc(void) const { return *MCID; }; [all...] |
HexagonMCInst.cpp | 33 const uint64_t F = MCID->TSFlags; 40 return (!MCID->isPseudo() && 52 const uint64_t F = MCID->TSFlags; 58 const uint64_t F = MCID->TSFlags; 64 const uint64_t F = MCID->TSFlags; 70 const uint64_t F = MCID->TSFlags; 118 const uint64_t F = MCID->TSFlags; 124 const uint64_t F = MCID->TSFlags; 130 const uint64_t F = MCID->TSFlags; 136 const uint64_t F = MCID->TSFlags [all...] |
/external/llvm/include/llvm/MC/ |
MCInstrDesc.h | 99 namespace MCID { 210 return Flags & (1 << MCID::Variadic); 216 return Flags & (1 << MCID::HasOptionalDef); 223 return Flags & (1 << MCID::Pseudo); 228 return Flags & (1 << MCID::Return); 233 return Flags & (1 << MCID::Call); 240 return Flags & (1 << MCID::Barrier); 250 return Flags & (1 << MCID::Terminator); 258 return Flags & (1 << MCID::Branch); 264 return Flags & (1 << MCID::IndirectBranch) [all...] |
/external/llvm/lib/Target/SystemZ/ |
SystemZInstrBuilder.h | 31 const MCInstrDesc &MCID = MI->getDesc(); 33 if (MCID.mayLoad()) 35 if (MCID.mayStore())
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/external/llvm/lib/Target/PowerPC/ |
PPCHazardRecognizers.cpp | 31 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 32 if (!MCID) 35 if (!MCID->mayLoad()) 57 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 58 if (!MCID) 61 if (!MCID->isBranch()) 87 bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID, 92 unsigned IIC = MCID->getSchedClass(); 125 if (NSlots == 1 && PPC::getNonRecordFormOpcode(MCID->getOpcode()) != -1) 149 const MCInstrDesc *MCID = DAG->getInstrDesc(SU) [all...] |
PPCHazardRecognizers.h | 33 bool mustComeFirst(const MCInstrDesc *MCID, unsigned &NSlots);
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/external/llvm/include/llvm/CodeGen/ |
MachineInstrBuilder.h | 230 const MCInstrDesc &MCID) { 231 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL)); 239 const MCInstrDesc &MCID, 241 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL)) 252 const MCInstrDesc &MCID, 255 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); 263 const MCInstrDesc &MCID, 266 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); 274 const MCInstrDesc &MCID, 278 return BuildMI(BB, MII, DL, MCID, DestReg) [all...] |
MachineInstr.h | 71 const MCInstrDesc *MCID; // Instruction descriptor. 113 MachineInstr(MachineFunction&, const MCInstrDesc &MCID, 266 const MCInstrDesc &getDesc() const { return *MCID; } 270 int getOpcode() const { return MCID->Opcode; } 384 return hasProperty(MCID::Variadic, Type); 390 return hasProperty(MCID::HasOptionalDef, Type); 397 return hasProperty(MCID::Pseudo, Type); 401 return hasProperty(MCID::Return, Type); 405 return hasProperty(MCID::Call, Type); 412 return hasProperty(MCID::Barrier, Type) [all...] |
/external/llvm/lib/Target/ARM/ |
ARMCodeEmitter.cpp | 101 const MCInstrDesc &MCID, 107 const MCInstrDesc &MCID) const; 453 const MCInstrDesc &MCID = MI.getDesc(); 455 unsigned Reloc = ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm) 766 const MCInstrDesc &MCID = MI.getDesc(); 775 Binary |= getAddrModeSBit(MI, MCID); [all...] |
ARMHazardRecognizer.cpp | 22 const MCInstrDesc &MCID = MI->getDesc(); 23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; 26 unsigned Opcode = MCID.getOpcode(); 43 const MCInstrDesc &MCID = MI->getDesc(); 44 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
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Thumb2SizeReduction.cpp | 213 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) { 214 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs) 549 const MCInstrDesc &MCID = MI->getDesc(); 550 if (MCID.hasOptionalDef() && 551 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR) 698 const MCInstrDesc &MCID = MI->getDesc(); 699 if (MCID.hasOptionalDef()) { 700 unsigned NumOps = MCID.getNumOperands(); 726 unsigned NumOps = MCID.getNumOperands(); 728 if (i < NumOps && MCID.OpInfo[i].isOptionalDef() [all...] |
MLxExpansionPass.cpp | 187 const MCInstrDesc &MCID = MI->getDesc(); 188 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; 191 unsigned Opcode = MCID.getOpcode(); 344 const MCInstrDesc &MCID = MI->getDesc(); 352 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; 362 if (!TII->isFpMLxInstruction(MCID.getOpcode(),
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Thumb2ITBlockPass.cpp | 142 const MCInstrDesc &MCID = MI->getDesc(); 144 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
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/external/llvm/lib/CodeGen/ |
ScoreboardHazardRecognizer.cpp | 129 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 130 if (!MCID) { 134 unsigned idx = MCID->getSchedClass(); 185 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 186 assert(MCID && "The scheduler must filter non-machineinstrs"); 187 if (DAG->TII->isZeroCost(MCID->Opcode)) 194 unsigned idx = MCID->getSchedClass();
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MachineInstr.cpp | 538 if (MCID->ImplicitDefs) 539 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 541 if (MCID->ImplicitUses) 542 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses) 551 : MCID(&tid), Parent(nullptr), Operands(nullptr), NumOperands(0), 555 if (unsigned NumOps = MCID->getNumOperands() + 556 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) { 568 : MCID(&MI.getDesc()), Parent(nullptr), Operands(nullptr), NumOperands(0), 640 assert(MCID && "Cannot add operands before providing an instr descriptor") [all...] |
TargetInstrInfo.cpp | 42 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, 45 if (OpNum >= MCID.getNumOperands()) 48 short RegClass = MCID.OpInfo[OpNum].RegClass; 49 if (MCID.OpInfo[OpNum].isLookupPtrRegClass()) 123 const MCInstrDesc &MCID = MI->getDesc(); 124 bool HasDef = MCID.getNumDefs(); 186 const MCInstrDesc &MCID = MI->getDesc(); 187 if (!MCID.isCommutable()) 191 SrcOpIdx1 = MCID.getNumDefs(); 221 const MCInstrDesc &MCID = MI->getDesc() [all...] |
MachineVerifier.cpp | 774 const MCInstrDesc &MCID = MI->getDesc(); 775 if (MI->getNumOperands() < MCID.getNumOperands()) { 777 *OS << MCID.getNumOperands() << " operands expected, but " 818 const MCInstrDesc &MCID = MI->getDesc(); 820 // The first MCID.NumDefs operands must be explicit register defines 821 if (MONum < MCID.getNumDefs()) { 822 const MCOperandInfo &MCOI = MCID.OpInfo[MONum]; 829 } else if (MONum < MCID.getNumOperands()) { 830 const MCOperandInfo &MCOI = MCID.OpInfo[MONum]; 834 !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) [all...] |
/external/llvm/lib/Target/X86/ |
X86InstrBuilder.h | 153 const MCInstrDesc &MCID = MI->getDesc(); 155 if (MCID.mayLoad()) 157 if (MCID.mayStore())
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/external/llvm/lib/Target/AArch64/ |
AArch64ConditionalCompares.cpp | 593 const MCInstrDesc &MCID = TII->get(Opc); 596 MRI->createVirtualRegister(TII->getRegClass(MCID, 0, TRI, *MF)); 598 BuildMI(*Head, Head->end(), TermDL, MCID) 605 TII->getRegClass(MCID, 1, TRI, *MF)); 650 const MCInstrDesc &MCID = TII->get(Opc); 652 TII->getRegClass(MCID, 0, TRI, *MF)); 655 TII->getRegClass(MCID, 1, TRI, *MF)); 657 BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), MCID)
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AArch64RegisterInfo.cpp | 294 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri); 297 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF)); 300 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
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/external/chromium_org/third_party/skia/experimental/PdfViewer/pdfparser/native/pdfapi/ |
SkPdfMarkedContentReferenceDictionary_autogen.cpp | 59 int64_t SkPdfMarkedContentReferenceDictionary::MCID(SkPdfNativeDoc* doc) { 60 SkPdfNativeObject* ret = get("MCID", ""); 68 return get("MCID", "") != NULL;
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/external/skia/experimental/PdfViewer/pdfparser/native/pdfapi/ |
SkPdfMarkedContentReferenceDictionary_autogen.cpp | 59 int64_t SkPdfMarkedContentReferenceDictionary::MCID(SkPdfNativeDoc* doc) { 60 SkPdfNativeObject* ret = get("MCID", ""); 68 return get("MCID", "") != NULL;
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/external/llvm/lib/CodeGen/SelectionDAG/ |
ScheduleDAGFast.cpp | 258 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); 259 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { 260 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { 265 if (MCID.isCommutable()) 436 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); 437 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); 438 unsigned NumRes = MCID.getNumDefs(); 439 for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { 514 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); 515 if (!MCID.ImplicitDefs [all...] |
InstrEmitter.cpp | 320 const MCInstrDesc &MCID = MIB->getDesc(); 321 bool isOptDef = IIOpNum < MCID.getNumOperands() && 322 MCID.OpInfo[IIOpNum].isOptionalDef(); 357 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1; [all...] |
/external/llvm/lib/Target/Mips/ |
MipsInstrInfo.cpp | 102 const MCInstrDesc &MCID = get(Opc); 103 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
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