| /external/llvm/include/llvm/MC/ |
| MCInstBuilder.h | 33 Inst.addOperand(MCOperand::CreateReg(Reg));
39 Inst.addOperand(MCOperand::CreateImm(Val));
45 Inst.addOperand(MCOperand::CreateFPImm(Val));
51 Inst.addOperand(MCOperand::CreateExpr(Val));
57 Inst.addOperand(MCOperand::CreateInst(Val));
|
| MCInst.h | 10 // This file contains the declaration of the MCInst and MCOperand classes, which
31 /// MCOperand - Instances of this class represent operands of the MCInst class.
33 class MCOperand {
53 MCOperand() : Kind(kInvalid), FPImmVal(0.0) {}
111 static MCOperand CreateReg(unsigned Reg) {
112 MCOperand Op;
117 static MCOperand CreateImm(int64_t Val) {
118 MCOperand Op;
123 static MCOperand CreateFPImm(double Val) {
124 MCOperand Op
[all...] |
| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| AMDGPUMCCodeEmitter.h | 24 class MCOperand;
35 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64MCInstLower.h | 21 class MCOperand;
38 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const;
41 MCOperand lowerSymbolOperandDarwin(const MachineOperand &MO,
43 MCOperand lowerSymbolOperandELF(const MachineOperand &MO,
45 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
|
| /external/llvm/lib/Target/XCore/ |
| XCoreMCInstLower.h | 18 class MCOperand;
34 MCOperand LowerOperand(const MachineOperand& MO, unsigned offset = 0) const;
37 MCOperand LowerSymbolOperand(const MachineOperand &MO,
|
| XCoreMCInstLower.cpp | 35 MCOperand XCoreMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
71 return MCOperand::CreateExpr(MCSym);
78 return MCOperand::CreateExpr(Add);
81 MCOperand XCoreMCInstLower::LowerOperand(const MachineOperand &MO,
90 return MCOperand::CreateReg(MO.getReg());
92 return MCOperand::CreateImm(MO.getImm() + offset);
104 return MCOperand();
112 MCOperand MCOp = LowerOperand(MO);
|
| /external/llvm/lib/Target/Mips/ |
| MipsMCInstLower.h | 20 class MCOperand;
35 MCOperand LowerOperand(const MachineOperand& MO, unsigned offset = 0) const;
38 MCOperand LowerSymbolOperand(const MachineOperand &MO,
40 MCOperand createSub(MachineBasicBlock *BB1, MachineBasicBlock *BB2,
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZMCInstLower.h | 19 class MCOperand;
35 // Return an MCOperand for MO.
36 MCOperand lowerOperand(const MachineOperand& MO) const;
|
| SystemZMCInstLower.cpp | 77 MCOperand SystemZMCInstLower::lowerOperand(const MachineOperand &MO) const {
80 return MCOperand::CreateReg(MO.getReg());
83 return MCOperand::CreateImm(MO.getImm());
87 return MCOperand::CreateExpr(getExpr(MO, Kind));
|
| /external/llvm/lib/Target/Sparc/ |
| SparcMCInstLower.cpp | 31 static MCOperand LowerSymbolOperand(const MachineInstr *MI,
66 return MCOperand::CreateExpr(expr);
69 static MCOperand LowerOperand(const MachineInstr *MI,
77 return MCOperand::CreateReg(MO.getReg());
80 return MCOperand::CreateImm(MO.getImm());
92 return MCOperand();
104 MCOperand MCOp = LowerOperand(MI, MO, AP);
|
| SparcAsmPrinter.cpp | 79 static MCOperand createSparcMCOperand(SparcMCExpr::VariantKind Kind,
84 return MCOperand::CreateExpr(expr);
87 static MCOperand createPCXCallOP(MCSymbol *Label,
92 static MCOperand createPCXRelExprOp(SparcMCExpr::VariantKind Kind,
107 return MCOperand::CreateExpr(expr);
111 MCOperand &Callee,
121 MCOperand &Imm, MCOperand &RD,
132 MCOperand &RS1, MCOperand &Src2, MCOperand &RD
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMMCInstLower.cpp | 27 MCOperand ARMAsmPrinter::GetSymbolRef(const MachineOperand &MO,
64 return MCOperand::CreateExpr(Expr);
69 MCOperand &MCOp) {
77 MCOp = MCOperand::CreateReg(MO.getReg());
80 MCOp = MCOperand::CreateImm(MO.getImm());
83 MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
108 MCOp = MCOperand::CreateFPImm(Val.convertToDouble());
125 MCOperand MCOp;
|
| ARMInstrInfo.cpp | 40 NopInst.addOperand(MCOperand::CreateImm(0));
41 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
42 NopInst.addOperand(MCOperand::CreateReg(0));
45 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
46 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
47 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
48 NopInst.addOperand(MCOperand::CreateReg(0));
49 NopInst.addOperand(MCOperand::CreateReg(0));
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.cpp | 183 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum));
251 MCOperand baseReg = MCOperand::CreateReg(baseRegNo);
254 MCOperand segmentReg;
255 segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
276 MCOperand baseReg = MCOperand::CreateReg(baseRegNo);
359 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4)));
362 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4)));
365 mcInst.addOperand(MCOperand::CreateReg(X86::ZMM0 + (immediate >> 4)))
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPUMCInstLower.cpp | 36 MCOperand MCOp;
44 MCOp = MCOperand::CreateFPImm(FloatValue.convertToFloat());
48 MCOp = MCOperand::CreateImm(MO.getImm());
51 MCOp = MCOperand::CreateReg(MO.getReg());
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUMCInstLower.cpp | 36 MCOperand MCOp;
44 MCOp = MCOperand::CreateFPImm(FloatValue.convertToFloat());
48 MCOp = MCOperand::CreateImm(MO.getImm());
51 MCOp = MCOperand::CreateReg(MO.getReg());
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonMCInstLower.cpp | 27 static MCOperand GetSymbolRef(const MachineOperand& MO, const MCSymbol* Symbol,
38 return (MCOperand::CreateExpr(ME));
49 MCOperand MCO;
58 MCO = MCOperand::CreateReg(MO.getReg());
64 MCO = MCOperand::CreateImm(*Val.bitcastToAPInt().getRawData());
68 MCO = MCOperand::CreateImm(MO.getImm());
71 MCO = MCOperand::CreateExpr
|
| /external/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 432 MI.addOperand(MCOperand::CreateImm(tmp));
438 MI.addOperand(MCOperand::CreateImm(0));
472 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
475 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
477 MI.addOperand(MCOperand::CreateImm(Imm));
511 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
514 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
516 MI.addOperand(MCOperand::CreateImm(Imm));
553 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
556 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430MCInstLower.cpp | 95 MCOperand MSP430MCInstLower::
110 return MCOperand::CreateExpr(Expr);
119 MCOperand MCOp;
127 MCOp = MCOperand::CreateReg(MO.getReg());
130 MCOp = MCOperand::CreateImm(MO.getImm());
133 MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
|
| MSP430MCInstLower.h | 19 class MCOperand;
36 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
| AMDGPUMCCodeEmitter.h | 23 class MCOperand;
31 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCInst.h | 21 class MCOperand;
75 const MCOperand& getNewValue() const;
|
| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| AMDGPUMCCodeEmitter.h | 23 class MCOperand;
31 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
|
| /external/llvm/lib/Target/MSP430/InstPrinter/ |
| MSP430InstPrinter.cpp | 37 const MCOperand &Op = MI->getOperand(OpNo);
49 const MCOperand &Op = MI->getOperand(OpNo);
63 const MCOperand &Base = MI->getOperand(OpNo);
64 const MCOperand &Disp = MI->getOperand(OpNo+1);
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCCodeEmitter.cpp | 55 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
216 AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
230 const MCOperand &MO = MI.getOperand(OpIdx);
251 const MCOperand &MO = MI.getOperand(OpIdx);
278 const MCOperand &MO = MI.getOperand(OpIdx);
279 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
287 assert(MO.isExpr() && "Unable to encode MCOperand!");
304 const MCOperand &MO = MI.getOperand(OpIdx);
326 const MCOperand &MO = MI.getOperand(OpIdx);
355 const MCOperand &MO = MI.getOperand(OpIdx)
[all...] |
