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Searched
refs:NumVecs
(Results
1 - 4
of
4
) sorted by null
/external/llvm/lib/Target/AArch64/
AArch64ISelDAGToDAG.cpp
140
SDNode *SelectTable(SDNode *N, unsigned
NumVecs
, unsigned Opc, bool isExt);
144
SDNode *SelectLoad(SDNode *N, unsigned
NumVecs
, unsigned Opc,
146
SDNode *SelectPostLoad(SDNode *N, unsigned
NumVecs
, unsigned Opc,
148
SDNode *SelectLoadLane(SDNode *N, unsigned
NumVecs
, unsigned Opc);
149
SDNode *SelectPostLoadLane(SDNode *N, unsigned
NumVecs
, unsigned Opc);
151
SDNode *SelectStore(SDNode *N, unsigned
NumVecs
, unsigned Opc);
152
SDNode *SelectPostStore(SDNode *N, unsigned
NumVecs
, unsigned Opc);
153
SDNode *SelectStoreLane(SDNode *N, unsigned
NumVecs
, unsigned Opc);
154
SDNode *SelectPostStoreLane(SDNode *N, unsigned
NumVecs
, unsigned Opc);
878
SDNode *AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned
NumVecs
,
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AArch64ISelLowering.cpp
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/external/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp
214
/// SelectVLD - Select NEON load intrinsics.
NumVecs
should be
217
/// For
NumVecs
<= 2, QOpcodes1 is not used.
218
SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned
NumVecs
,
222
/// SelectVST - Select NEON store intrinsics.
NumVecs
should
225
/// For
NumVecs
<= 2, QOpcodes1 is not used.
226
SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned
NumVecs
,
230
/// SelectVLDSTLane - Select NEON load/store lane intrinsics.
NumVecs
should
234
bool isUpdating, unsigned
NumVecs
,
237
/// SelectVLDDup - Select NEON load-duplicate intrinsics.
NumVecs
240
SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned
NumVecs
,
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ARMISelLowering.cpp
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Completed in 274 milliseconds