HomeSort by relevance Sort by last modified time
    Searched refs:OffsetReg (Results 1 - 13 of 13) sorted by null

  /external/llvm/lib/Target/R600/
AMDGPUInstrInfo.cpp 139 unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
140 if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
145 Address, OffsetReg);
154 unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
155 if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
161 OffsetReg);
R600InstrInfo.h 43 unsigned OffsetReg,
49 unsigned OffsetReg,
224 unsigned OffsetReg) const override;
229 unsigned OffsetReg) const override;
AMDGPUInstrInfo.h 170 unsigned OffsetReg) const = 0;
178 unsigned OffsetReg) const = 0;
SIInstrInfo.h 164 unsigned OffsetReg) const override;
170 unsigned OffsetReg) const override;
R600InstrInfo.cpp     [all...]
SIInstrInfo.cpp     [all...]
  /external/llvm/lib/Target/Sparc/AsmParser/
SparcAsmParser.cpp 168 unsigned OffsetReg;
220 return Mem.OffsetReg;
354 unsigned offsetReg = Op->getReg();
357 Op->Mem.OffsetReg = offsetReg;
366 Op->Mem.OffsetReg = 0;
378 Op->Mem.OffsetReg = 0;
  /external/llvm/lib/Target/ARM/
Thumb2SizeReduction.cpp 471 unsigned OffsetReg = 0;
474 OffsetReg = MI->getOperand(2).getReg();
502 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!");
505 MIB.addReg(OffsetReg, getKillRegState(OffsetKill));
    [all...]
Thumb2InstrInfo.cpp 524 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
525 if (OffsetReg != 0) {
  /external/llvm/lib/Target/Mips/
MipsSEInstrInfo.cpp 595 // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
603 unsigned OffsetReg = I->getOperand(0).getReg();
615 .addReg(SP).addReg(OffsetReg);
MipsISelLowering.cpp     [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp     [all...]
  /external/llvm/lib/Target/X86/
X86ISelLowering.cpp     [all...]

Completed in 174 milliseconds