/system/core/libpixelflinger/codeflinger/ |
ARMAssemblerInterface.h | 124 uint32_t Op2) = 0; 224 ADC(int cc, int s, int Rd, int Rn, uint32_t Op2) { 225 dataProcessing(opADC, cc, s, Rd, Rn, Op2); 228 ADD(int cc, int s, int Rd, int Rn, uint32_t Op2) { 229 dataProcessing(opADD, cc, s, Rd, Rn, Op2); 232 AND(int cc, int s, int Rd, int Rn, uint32_t Op2) { 233 dataProcessing(opAND, cc, s, Rd, Rn, Op2); 236 BIC(int cc, int s, int Rd, int Rn, uint32_t Op2) { 237 dataProcessing(opBIC, cc, s, Rd, Rn, Op2); 240 EOR(int cc, int s, int Rd, int Rn, uint32_t Op2) { [all...] |
ARMAssemblerInterface.cpp | 79 int Rd, int Rn, uint32_t Op2) 81 dataProcessing(opADD, cc, s, Rd, Rn, Op2); 84 int Rd, int Rn, uint32_t Op2) 86 dataProcessing(opSUB, cc, s, Rd, Rn, Op2);
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Arm64Assembler.cpp | 341 int s, int Rd, int Rn, uint32_t Op2) 356 if(Op2 == OPERAND_REG_IMM && mAddrMode.reg_imm_shift > 31) 364 if(Op2 == OPERAND_IMM) 369 Op2 = mTmpReg2; 378 if(Op2 == OPERAND_REG_IMM) 384 else if(Op2 < OPERAND_REG) 388 Rm = Op2; 409 int s, int Rd, int Rn, uint32_t Op2) 420 dataProcessingCommon(opcode, s, Wd, Rn, Op2); 424 dataProcessingCommon(opSUB, 1, mTmpReg3, Rn, Op2); [all...] |
ARMAssemblerProxy.cpp | 161 int Rd, int Rn, uint32_t Op2) 163 mTarget->dataProcessing(opcode, cc, s, Rd, Rn, Op2); 303 void ARMAssemblerProxy::ADDR_ADD(int cc, int s, int Rd, int Rn, uint32_t Op2){ 304 mTarget->ADDR_ADD(cc, s, Rd, Rn, Op2); 306 void ARMAssemblerProxy::ADDR_SUB(int cc, int s, int Rd, int Rn, uint32_t Op2){ 307 mTarget->ADDR_SUB(cc, s, Rd, Rn, Op2);
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ARMAssemblerProxy.h | 81 uint32_t Op2); 154 int Rn, uint32_t Op2); 156 int Rn, uint32_t Op2);
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MIPSAssembler.cpp | 418 int s, int Rd, int Rn, uint32_t Op2) 434 if (dataProcAdrModes(Op2, src) == SRC_REG) { 443 if (dataProcAdrModes(Op2, src, true) == SRC_REG) { 452 if (dataProcAdrModes(Op2, src, true) == SRC_REG) { 460 if (dataProcAdrModes(Op2, src) == SRC_REG) { 468 if (dataProcAdrModes(Op2, src) == SRC_REG) { 476 if (dataProcAdrModes(Op2, src) == SRC_IMM) { 486 if (dataProcAdrModes(Op2, src) == SRC_IMM) { 495 if (Op2 < AMODE_REG) { // op2 is reg # in this cas [all...] |
Arm64Assembler.h | 100 uint32_t Op2); 126 int Rn, uint32_t Op2); 128 int Rn, uint32_t Op2); 189 int Rd, int Rn, uint32_t Op2);
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/external/llvm/lib/Target/XCore/Disassembler/ |
XCoreDisassembler.cpp | 254 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { 267 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2); 272 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, 282 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2); 360 unsigned Op1, Op2; 361 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 366 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 373 unsigned Op1, Op2; 374 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 379 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder) [all...] |
/external/llvm/lib/Target/XCore/ |
XCoreSelectionDAGInfo.h | 31 SDValue Op1, SDValue Op2,
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/external/llvm/include/llvm/Target/ |
TargetSelectionDAGInfo.h | 59 SDValue Op1, SDValue Op2, 76 SDValue Op1, SDValue Op2, 92 SDValue Op1, SDValue Op2, 106 SDValue Op1, SDValue Op2, 147 SDValue Op1, SDValue Op2,
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/external/llvm/lib/Target/ARM/ |
ARMSelectionDAGInfo.h | 54 SDValue Op1, SDValue Op2,
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/external/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | [all...] |
SelectionDAG.h | 606 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, 612 Ops.push_back(Op2); [all...] |
FastISel.h | 280 unsigned Op2, bool Op2IsKill);
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/external/llvm/lib/Target/AArch64/InstPrinter/ |
AArch64InstPrinter.cpp | 72 const MCOperand &Op2 = MI->getOperand(2); 77 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { 113 if (Op2.isImm() && Op3.isImm()) { 116 int64_t immr = Op2.getImm(); 147 if (Op2.getImm() > Op3.getImm()) { 150 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1; 158 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1; 165 const MCOperand &Op2 = MI->getOperand(2) [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeVectorOps.cpp | 672 SDValue Op2 = Op.getOperand(2); 675 && Op1.getValueType() == Op2.getValueType() && "Invalid type"); 708 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2); 715 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask); 716 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2); 849 SDValue Op2 = Op.getOperand(2); 877 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2); [all...] |
SelectionDAG.cpp | 299 /// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 302 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 304 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 308 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 323 /// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 326 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 328 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 333 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 812 SDValue Op1, SDValue Op2, 817 SDValue Ops[] = { Op1, Op2 }; [all...] |
/external/llvm/lib/Target/X86/AsmParser/ |
X86AsmParser.cpp | 172 ICToken Op2 = OperandStack.pop_back_val(); 179 Val = Op1.second + Op2.second; 183 Val = Op1.second - Op2.second; 187 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && 189 Val = Op1.second * Op2.second; 193 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && 195 assert (Op2.second != 0 && "Division by zero!"); 196 Val = Op1.second / Op2.second; 200 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && 202 Val = Op1.second | Op2.second [all...] |
/external/llvm/lib/Analysis/ |
ConstantFolding.cpp | [all...] |
/external/llvm/lib/Transforms/Scalar/ |
LoopRerollPass.cpp | [all...] |
Scalarizer.cpp | 391 Scatterer Op2 = scatter(&SI, SI.getOperand(2)); 393 assert(Op2.size() == NumElems && "Mismatched select"); 401 Res[I] = Builder.CreateSelect(Op0[I], Op1[I], Op2[I], 406 Res[I] = Builder.CreateSelect(Op0, Op1[I], Op2[I],
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/external/llvm/lib/Target/AArch64/Utils/ |
AArch64BaseInfo.cpp | 794 // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name, where the bits 804 uint32_t Op0 = 3, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; 809 Ops[4].getAsInteger(10, Op2); 810 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; 849 uint32_t Op2 = Bits & 0x7; 862 + "_c" + utostr(CRm) + "_" + utostr(Op2);
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/external/llvm/include/llvm/Analysis/ |
ScalarEvolution.h | 607 const SCEV *getAddExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, 612 Ops.push_back(Op2); 625 const SCEV *getMulExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, 630 Ops.push_back(Op2); [all...] |
/external/llvm/include/llvm/Transforms/Utils/ |
BuildLibCalls.h | 88 /// 'Op2' and return one value with the same type. If 'Op1/Op2' are long 89 /// double, 'l' is added as the suffix of name, if 'Op1/Op2' are float, we 91 Value *EmitBinaryFloatFnCall(Value *Op1, Value *Op2, StringRef Name,
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/external/llvm/lib/Target/Hexagon/ |
HexagonPeephole.cpp | 300 MachineOperand Op2 = MI->getOperand(S2); 301 ChangeOpInto(MI->getOperand(S1), Op2);
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