| /frameworks/opt/vcard/tests/src/com/android/vcard/tests/ |
| VCardParserTests.java | 38 private enum Order {
47 private final List<Order> mHistory = new ArrayList<Order>();
48 private final List<Order> mExpectedOrder = new ArrayList<Order>();
50 public MockVCardInterpreter addExpectedOrder(Order order) {
51 mExpectedOrder.add(order);
55 private void inspectOrder(Order order) {
[all...] |
| /external/chromium_org/third_party/opus/src/silk/float/ |
| corrMatrix_FLP.c | 40 const silk_float *x, /* I x vector [L+order-1] used to create X */
43 const opus_int Order, /* I Max lag for correlation */
44 silk_float *Xt /* O X'*t correlation vector [order] */
50 ptr1 = &x[ Order - 1 ]; /* Points to first sample of column 0 of X: X[:,0] */
51 for( lag = 0; lag < Order; lag++ ) {
60 const silk_float *x, /* I x vector [ L+order-1 ] used to create X */
62 const opus_int Order, /* I Max lag for correlation */
63 silk_float *XX /* O X'*X correlation matrix [order x order] */
70 ptr1 = &x[ Order - 1 ]; /* First sample of column 0 of X *
[all...] |
| LPC_analysis_filter_FLP.c | 39 /* first Order output samples are set to zero */
42 /* 16th order LPC analysis filter, does not write first 16 samples */
80 /* 12th order LPC analysis filter, does not write first 12 samples */
114 /* 10th order LPC analysis filter, does not write first 10 samples */
146 /* 8th order LPC analysis filter, does not write first 8 samples */
176 /* 6th order LPC analysis filter, does not write first 6 samples */
208 /* first Order output samples are set to zero */
215 const opus_int Order /* I LPC order */
218 silk_assert( Order <= length )
[all...] |
| /external/libopus/silk/float/ |
| corrMatrix_FLP.c | 40 const silk_float *x, /* I x vector [L+order-1] used to create X */
43 const opus_int Order, /* I Max lag for correlation */
44 silk_float *Xt /* O X'*t correlation vector [order] */
50 ptr1 = &x[ Order - 1 ]; /* Points to first sample of column 0 of X: X[:,0] */
51 for( lag = 0; lag < Order; lag++ ) {
60 const silk_float *x, /* I x vector [ L+order-1 ] used to create X */
62 const opus_int Order, /* I Max lag for correlation */
63 silk_float *XX /* O X'*X correlation matrix [order x order] */
70 ptr1 = &x[ Order - 1 ]; /* First sample of column 0 of X *
[all...] |
| LPC_analysis_filter_FLP.c | 39 /* first Order output samples are set to zero */
42 /* 16th order LPC analysis filter, does not write first 16 samples */
80 /* 12th order LPC analysis filter, does not write first 12 samples */
114 /* 10th order LPC analysis filter, does not write first 10 samples */
146 /* 8th order LPC analysis filter, does not write first 8 samples */
176 /* 6th order LPC analysis filter, does not write first 6 samples */
208 /* first Order output samples are set to zero */
215 const opus_int Order /* I LPC order */
218 silk_assert( Order <= length )
[all...] |
| /external/llvm/lib/CodeGen/ |
| AllocationOrder.cpp | 1 //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
10 // This file implements an allocation order for virtual registers.
12 // The preferred allocation order for a virtual register depends on allocation
36 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
37 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM);
50 assert(std::find(Order.begin(), Order.end(), Hints[I]) != Order.end() &&
51 "Target hint is outside allocation order.");
|
| AllocationOrder.h | 1 //===-- llvm/CodeGen/AllocationOrder.h - Allocation Order -*- C++ -*-------===//
10 // This file implements an allocation order for virtual registers.
12 // The preferred allocation order for a virtual register depends on allocation
30 ArrayRef<MCPhysReg> Order;
42 /// Get the allocation order without reordered hints.
43 ArrayRef<MCPhysReg> getOrder() const { return Order; }
45 /// Return the next physical register in the allocation order, or 0.
52 Limit = Order.size();
54 unsigned Reg = Order[Pos++];
62 /// Limit'th register in the RegisterClassInfo allocation order
[all...] |
| RegisterClassInfo.cpp | 76 /// compute - Compute the preferred allocation order for RC with reserved
78 /// aliases ordered according to the CSR order specified by the target.
85 if (!RCI.Order)
86 RCI.Order.reset(new MCPhysReg[NumRegs]);
95 // allocation order, we can simply use begin/end here.
99 // Remove reserved registers from the allocation order.
111 RCI.Order[N++] = PhysReg;
116 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
118 // CSR aliases go after the volatile registers, preserve the target's order.
124 RCI.Order[N++] = PhysReg
[all...] |
| TargetRegisterInfo.cpp | 133 ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF);
134 for (unsigned i = 0; i != Order.size(); ++i)
135 R.set(Order[i]);
265 ArrayRef<MCPhysReg> Order,
287 // Check that Phys is in the allocation order. We shouldn't heed hints
288 // from VirtReg's register class if they aren't in the allocation order. The
290 if (std::find(Order.begin(), Order.end(), Phys) == Order.end())
|
| /external/chromium_org/skia/ext/ |
| recursive_gaussian_convolution.h | 21 enum Order {
29 SK_API RecursiveFilter(float sigma, Order order);
31 Order order() const { return order_; } function in class:skia::RecursiveFilter
35 Order order_;
|
| recursive_gaussian_convolution.cc | 32 template<RecursiveFilter::Order order>
39 switch (order) {
54 template<RecursiveFilter::Order order>
60 switch (order) {
73 template<RecursiveFilter::Order order, bool absolute_values>
93 if (order == RecursiveFilter::FUNCTION)
98 w[3] = ForwardFilter<order>(
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SDNodeDbgValue.h | 51 unsigned Order;
58 Offset(off), DL(dl), Order(O),
68 mdPtr(mdP), IsIndirect(false), Offset(off), DL(dl), Order(O),
76 mdPtr(mdP), IsIndirect(false), Offset(off), DL(dl), Order(O),
109 // Returns the SDNodeOrder. This is the order of the preceding node in the
111 unsigned getOrder() { return Order; }
|
| /external/aac/libAACdec/src/ |
| aacdec_tns.h | 99 TNS_MAXIMUM_ORDER = 20, /* 12 for AAC-LC and AAC-SSR. Set to 20 for AAC-Main (AOT 1). Some broken encoders also do order 20 for AAC-LC :( */
113 UCHAR Order;
|
| aacdec_tns.cpp | 133 UCHAR n_filt,order; local
176 filter->Order = order = (UCHAR) FDKreadBits(bs, isLongFlag ? 5 : 3);
179 if (filter->Order > TNS_MAXIMUM_ORDER){
180 filter->Order = order = TNS_MAXIMUM_ORDER;
183 if (order)
200 for (i=0; i < order; i++)
216 static void CTns_Filter (FIXP_DBL *spec, int size, int inc, FIXP_TCC coeff [], int order)
218 // - Simple all-pole filter of order "order" defined b
[all...] |
| /external/deqp/framework/referencerenderer/ |
| rrVertexAttrib.cpp | 59 template<typename SrcScalarType, typename DstScalarType, typename Order>
65 dst[Order::T0] = DstScalarType(aligned[0]);
66 if (size >= 2) dst[Order::T1] = DstScalarType(aligned[1]);
67 if (size >= 3) dst[Order::T2] = DstScalarType(aligned[2]);
68 if (size >= 4) dst[Order::T3] = DstScalarType(aligned[3]);
71 template<typename SrcScalarType, typename Order>
79 dst[Order::T0] = float(aligned[0]) / float(range);
80 if (size >= 2) dst[Order::T1] = float(aligned[1]) / float(range);
81 if (size >= 3) dst[Order::T2] = float(aligned[2]) / float(range);
82 if (size >= 4) dst[Order::T3] = float(aligned[3]) / float(range)
[all...] |
| /external/llvm/test/MC/COFF/ |
| symbol-alias.s | 26 # Order is important here. Assign _bar_alias_alias before _bar_alias.
|
| /external/chromium_org/third_party/icu/source/test/intltest/ |
| tscoll.h | 26 struct Order
28 int32_t order; member in struct:IntlTestCollator::Order
51 Order *getOrders(CollationElementIterator &iter, int32_t &orderLength);
|
| tscoll.cpp | 408 LocalArray<Order> orders(getOrders(iter, orderLength));
433 if (o != orders[index].order) {
437 while (index > 0 && orders[--index].order == 0) {
441 if (o != orders[index].order) {
442 errln("Mismatched order at index %d: 0x%0:8X vs. 0x%0:8X", index,
443 orders[index].order, o);
461 while (index != 0 && orders[index - 1].order == 0)
501 IntlTestCollator::Order *IntlTestCollator::getOrders(CollationElementIterator &iter, int32_t &orderLength)
505 LocalArray<Order> orders(new Order[maxSize])
509 int32_t order; local
[all...] |
| /external/icu/icu4c/source/test/intltest/ |
| tscoll.h | 26 struct Order
28 int32_t order; member in struct:IntlTestCollator::Order
51 Order *getOrders(CollationElementIterator &iter, int32_t &orderLength);
|
| tscoll.cpp | 390 LocalArray<Order> orders(getOrders(iter, orderLength));
415 if (o != orders[index].order) {
419 while (index > 0 && orders[--index].order == 0) {
423 if (o != orders[index].order) {
424 errln("Mismatched order at index %d: 0x%0:8X vs. 0x%0:8X", index,
425 orders[index].order, o);
443 while (index != 0 && orders[index - 1].order == 0)
483 IntlTestCollator::Order *IntlTestCollator::getOrders(CollationElementIterator &iter, int32_t &orderLength)
487 LocalArray<Order> orders(new Order[maxSize])
491 int32_t order; local
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| RegisterClassInfo.h | 33 std::unique_ptr<MCPhysReg[]> Order;
40 return makeArrayRef(Order.get(), NumRegs);
90 /// getOrder - Returns the preferred allocation order for RC. The order
116 /// Get the minimum register cost in RC's allocation order.
|
| SelectionDAGNodes.h | 192 /// factors and non-volatile loads. In order to remain efficient, this only
460 void setIROrder(unsigned Order) { IROrder = Order; }
741 SDNode(unsigned Opc, unsigned Order, const DebugLoc dl, SDVTList VTs,
748 debugLoc(dl), IROrder(Order) {
758 SDNode(unsigned Opc, unsigned Order, const DebugLoc dl, SDVTList VTs)
762 IROrder(Order) {}
854 SDLoc(const Instruction *I, int Order) : Ptr(I), IROrder(Order) {
855 assert(Order >= 0 && "bad IROrder")
[all...] |
| ScheduleDAG.h | 52 Order ///< Any other ordering dependency.
85 /// Order - Additional information about Order dependencies.
120 : Dep(S, Order), Contents(), Latency(0) {
132 case Order:
179 /// isNormalMemory - Test if this is an Order dependence between two
183 return getKind() == Order && (Contents.OrdKind == MayAliasMem
187 /// isBarrier - Test if this is an Order dependence that is marked
190 return getKind() == Order && Contents.OrdKind == Barrier;
193 /// isMustAlias - Test if this is an Order dependence that is marke
[all...] |
| /external/lzma/CPP/7zip/UI/Common/ |
| ZipRegistry.h | 31 UInt32 Order;
42 BlockLogSize = NumThreads = Level = Dictionary = Order = UInt32(-1);
|
| /external/chromium_org/tools/python/google/httpd_config/ |
| httpd2_linux.conf | 80 Order allow,deny
|
