| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 702 /// PRE_INC Similar to the unindexed mode where the effective address is
[all...] |
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/lib/gcc/x86_64-w64-mingw32/4.8.3/plugin/include/ |
| rtl.def | 496 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
[all...] |
| genrtl.h | 1007 gen_rtx_fmt_e (PRE_INC, (MODE), (ARG0))
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 332 case ISD::PRE_INC: return "<pre-inc>";
|
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 809 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
845 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
865 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
[all...] |
| ARMISelLowering.cpp | 593 for (unsigned im = (unsigned)ISD::PRE_INC;
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 89 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal)
[all...] |
| PPCISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 728 for (unsigned IM = (unsigned)ISD::PRE_INC;
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 320 for (unsigned im = (unsigned)ISD::PRE_INC;
541 for (unsigned im = (unsigned)ISD::PRE_INC;
[all...] |
| AArch64ISelDAGToDAG.cpp | [all...] |
