| /external/llvm/include/llvm/Target/ |
| TargetOpcodes.h | 71 /// REG_SEQUENCE - This variadic instruction is used to form a register that
76 // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
79 /// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
82 REG_SEQUENCE = 12,
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelDAGToDAG.cpp | 138 case AMDGPU::REG_SEQUENCE: {
300 // 2 = 2 REG_SEQUENCE operands per element (value, subreg index)
333 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(),
354 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
383 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, SDLoc(N),
701 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, MVT::i64, Args);
|
| SIInstrInfo.cpp | 681 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
749 case AMDGPU::REG_SEQUENCE:
844 BuildMI(*MBB, MI, DL, get(TargetOpcode::REG_SEQUENCE), Dst)
[all...] |
| R600OptimizeVectorRegisters.cpp | 67 assert(MI->getOpcode() == AMDGPU::REG_SEQUENCE);
329 if (MI->getOpcode() != AMDGPU::REG_SEQUENCE) {
|
| SIFixSGPRCopies.cpp | 250 case AMDGPU::REG_SEQUENCE: {
255 DEBUG(dbgs() << "Fixing REG_SEQUENCE:\n");
|
| SIISelLowering.cpp | 481 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SubRegHi)
486 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SuperReg)
[all...] |
| R600ISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 718 return getOpcode() == TargetOpcode::REG_SEQUENCE;
757 case TargetOpcode::REG_SEQUENCE:
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ResourcePriorityQueue.cpp | 268 case TargetOpcode::REG_SEQUENCE:
308 case TargetOpcode::REG_SEQUENCE:
|
| InstrEmitter.cpp | 598 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
606 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
610 "REG_SEQUENCE must have an odd number of operands!");
726 // Handle REG_SEQUENCE specially.
727 if (Opc == TargetOpcode::REG_SEQUENCE) {
[all...] |
| ScheduleDAGRRList.cpp | 299 if (Opcode == TargetOpcode::REG_SEQUENCE) {
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonMachineScheduler.cpp | 56 case TargetOpcode::REG_SEQUENCE:
108 case TargetOpcode::REG_SEQUENCE:
|
| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 331 // INSERT_SUBREG or REG_SEQUENCE.
459 // Takes two SPR registers and creates a DPR by using a REG_SEQUENCE.
469 TII->get(TargetOpcode::REG_SEQUENCE), Out)
586 // REG_SEQUENCE pseudos that insert an SPR value into a DPR register or
607 // * REG_SEQUENCE: * If all except one of the input operands are
|
| ARMISelDAGToDAG.cpp | 244 /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 131 /// unchanged; otherwise a REG_SEQUENCE value is returned.
863 // First operand of REG_SEQUENCE is the desired RegClass.
874 CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, MVT::Untyped, Ops);
[all...] |
