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    Searched refs:Reg0 (Results 1 - 9 of 9) sorted by null

  /external/llvm/include/llvm/MC/
MCRegisterInfo.h 524 uint16_t Reg0;
527 MCRegUnitRootIterator() : Reg0(0), Reg1(0) {}
530 Reg0 = MCRI->RegUnitRoots[RegUnit][0];
536 return Reg0;
541 return Reg0;
547 Reg0 = Reg1;
  /external/llvm/lib/Target/Hexagon/
HexagonPeephole.cpp 249 unsigned Reg0 = Op0.getReg();
250 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
254 if (TargetRegisterInfo::isVirtualRegister(Reg0)) {
256 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {
  /external/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp     [all...]
Thumb2SizeReduction.cpp 641 unsigned Reg0 = MI->getOperand(0).getReg();
647 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1)
650 if (Reg0 != Reg2) {
653 if (Reg1 != Reg0)
660 } else if (Reg0 != Reg1) {
664 CommOpIdx1 != 1 || MI->getOperand(CommOpIdx2).getReg() != Reg0)
670 if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
    [all...]
ARMAsmPrinter.cpp 265 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
266 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
    [all...]
  /external/llvm/lib/CodeGen/
TargetInstrInfo.cpp 136 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
146 if (HasDef && Reg0 == Reg1 &&
149 Reg0 = Reg2;
151 } else if (HasDef && Reg0 == Reg2 &&
154 Reg0 = Reg1;
165 MI->getOperand(0).setReg(Reg0);
  /external/llvm/lib/Target/ARM/InstPrinter/
ARMInstPrinter.cpp     [all...]
  /external/llvm/lib/Target/Mips/
MipsSEFrameLowering.cpp 329 unsigned Reg0 =
335 std::swap(Reg0, Reg1);
338 MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
  /external/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 250 unsigned Reg0 = MI->getOperand(0).getReg();
260 if (Reg0 == Reg1) {
275 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
278 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
    [all...]

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