| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AsmBackend.cpp | 415 unsigned Reg2 = MRI.getLLVMRegNum(Inst2.getRegister(), true);
426 Reg2 = getXRegFromWReg(Reg2);
428 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 &&
431 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 &&
434 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 &&
437 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 &&
440 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 &&
445 Reg2 = getDRegFromBReg(Reg2);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsAsmPrinter.h | 67 void EmitInstrRegReg(unsigned Opcode, unsigned Reg1, unsigned Reg2);
69 void EmitInstrRegRegReg(unsigned Opcode, unsigned Reg1, unsigned Reg2,
72 void EmitMovFPIntPair(unsigned MovOpc, unsigned Reg1, unsigned Reg2,
|
| MipsAsmPrinter.cpp | 732 unsigned Reg2) {
741 Reg1 = Reg2;
742 Reg2 = Temp;
746 I.addOperand(MCOperand::CreateReg(Reg2));
751 unsigned Reg2, unsigned Reg3) {
755 I.addOperand(MCOperand::CreateReg(Reg2));
761 unsigned Reg2, unsigned FPReg1,
765 Reg1 = Reg2;
766 Reg2 = temp;
769 EmitInstrRegReg(MovOpc, Reg2, FPReg2)
[all...] |
| Mips16InstrInfo.h | 117 unsigned Reg1, unsigned Reg2) const;
|
| Mips16InstrInfo.cpp | 266 unsigned Reg1, unsigned Reg2) const {
270 // unsigned Reg2 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
273 // move reg2, sp
274 // add reg1, reg1, reg2
280 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
284 MIB3.addReg(Reg2, RegState::Kill);
|
| MipsISelLowering.cpp | 598 // addiu $reg2, $reg1, y-1
605 // addiu $reg2, $reg1, y-1
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 117 unsigned Reg2, bool isKill2) {
119 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
|
| /external/llvm/lib/CodeGen/ |
| AggressiveAntiDepBreaker.h | 101 // UnionGroups - Union Reg1's and Reg2's groups to form a new
104 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
|
| TargetInstrInfo.cpp | 138 unsigned Reg2 = MI->getOperand(Idx2).getReg();
149 Reg0 = Reg2;
151 } else if (HasDef && Reg0 == Reg2 &&
169 MI->getOperand(Idx1).setReg(Reg2);
|
| AggressiveAntiDepBreaker.cpp | 80 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2)
87 unsigned Group2 = GetGroup(Reg2);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | 631 unsigned Reg2 = CSI[idx + 1].getReg();
653 assert(AArch64::GPR64RegClass.contains(Reg2) &&
661 assert(AArch64::FPR64RegClass.contains(Reg2) &&
671 << TRI->getName(Reg2) << ") -> fi#(" << CSI[idx].getFrameIdx()
682 MIB.addReg(Reg2, getPrologueDeath(MF, Reg2))
706 unsigned Reg2 = CSI[i + 1].getReg();
724 assert(AArch64::GPR64RegClass.contains(Reg2) &&
731 assert(AArch64::FPR64RegClass.contains(Reg2) &&
740 << TRI->getName(Reg2) << ") -> fi#(" << CSI[i].getFrameIdx(
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 80 bool contains(unsigned Reg1, unsigned Reg2) const {
81 return contains(Reg1) && contains(Reg2);
|
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 81 bool contains(unsigned Reg1, unsigned Reg2) const {
82 return MC->contains(Reg1, Reg2);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 645 unsigned Reg2 = MI->getOperand(2).getReg();
648 || !isARMLowRegister(Reg2))
650 if (Reg0 != Reg2) {
678 unsigned Reg2 = MI->getOperand(2).getReg();
679 if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
[all...] |
| A15SDOptimizer.cpp | 84 unsigned Reg1, unsigned Reg2);
464 unsigned Reg1, unsigned Reg2) {
472 .addReg(Reg2)
|
| ARMFastISel.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 252 unsigned Reg2 = MI->getOperand(2).getReg();
275 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
279 .addReg(Reg2, getKillRegState(Reg2IsKill))
286 MI->getOperand(0).setReg(Reg2);
290 MI->getOperand(1).setReg(Reg2);
[all...] |
| /external/llvm/lib/MC/ |
| MCDwarf.cpp | [all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
