/external/llvm/lib/Target/R600/MCTargetDesc/ |
SIMCCodeEmitter.cpp | 79 unsigned RegClass = Desc.OpInfo[OpNo].RegClass; 80 return (AMDGPU::SSrc_32RegClassID == RegClass) || 81 (AMDGPU::SSrc_64RegClassID == RegClass) || 82 (AMDGPU::VSrc_32RegClassID == RegClass) || 83 (AMDGPU::VSrc_64RegClassID == RegClass);
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/external/llvm/include/llvm/CodeGen/ |
RegisterScavenging.h | 125 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const; 154 unsigned scavengeRegister(const TargetRegisterClass *RegClass, 156 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { 157 return scavengeRegister(RegClass, MBBI, SPAdj);
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RegisterClassInfo.h | 45 std::unique_ptr<RCInfo[]> RegClass; 71 const RCInfo &RCI = RegClass[RC->getID()];
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MachineRegisterInfo.h | 588 unsigned createVirtualRegister(const TargetRegisterClass *RegClass); [all...] |
/external/llvm/lib/Target/R600/ |
SIISelLowering.h | 38 unsigned RegClass) const; 40 unsigned RegClass, bool &ScalarSlotUsed) const;
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SIISelLowering.cpp | [all...] |
AMDGPUISelDAGToDAG.cpp | 132 int RegClass = Desc.OpInfo[OpIdx].RegClass; 133 if (RegClass == -1) 136 return TM.getRegisterInfo()->getRegClass(RegClass); 290 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, MVT::i32); 294 N->getOperand(0), RegClass);
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SIInstrInfo.cpp | 563 int RegClass = Desc.OpInfo[i].RegClass; 564 if (!RI.regClassCanUseImmediate(RegClass) && 584 int RegClass = Desc.OpInfo[i].RegClass; 585 if (RegClass != -1) { 590 const TargetRegisterClass *RC = RI.getRegClass(RegClass); 739 Desc.OpInfo[OpNo].RegClass == -1) 742 unsigned RCID = Desc.OpInfo[OpNo].RegClass; 762 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass; [all...] |
/external/llvm/lib/CodeGen/ |
RegisterClassInfo.cpp | 43 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); 80 RCInfo &RCI = RegClass[RC->getID()]; 116 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
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MachineRegisterInfo.cpp | 97 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ 98 assert(RegClass && "Cannot create register without RegClass!"); 99 assert(RegClass->isAllocatable() && 100 "Virtual register RegClass must be allocatable."); 105 VRegInfo[Reg].first = RegClass;
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TargetInstrInfo.cpp | 48 short RegClass = MCID.OpInfo[OpNum].RegClass; 50 return TRI->getPointerRegClass(MF, RegClass); 53 if (RegClass < 0) 57 return TRI->getRegClass(RegClass);
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/external/llvm/lib/Target/AArch64/ |
AArch64DeadRegisterDefinitionsPass.cpp | 98 switch (MI.getDesc().OpInfo[i].RegClass) {
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AArch64A57FPLoadBalancing.cpp | 475 unsigned RegClassID = G->getStart()->getDesc().OpInfo[0].RegClass;
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/external/llvm/include/llvm/MC/ |
MCInstrDesc.h | 60 /// RegClass - This specifies the register class enumeration of the operand 64 int16_t RegClass;
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/external/llvm/lib/Target/ARM/ |
ARMISelDAGToDAG.cpp | [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
R600InstrInfo.cpp | 253 switch (MI->getDesc().OpInfo->RegClass) {
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/external/mesa3d/src/gallium/drivers/radeon/ |
R600InstrInfo.cpp | 253 switch (MI->getDesc().OpInfo->RegClass) {
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/external/llvm/lib/Target/Mips/AsmParser/ |
MipsAsmParser.cpp | 177 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass); [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
FastISel.cpp | [all...] |
ScheduleDAGRRList.cpp | 280 unsigned &RegClass, unsigned &Cost, 293 RegClass = RC->getID(); 302 RegClass = RC->getID(); 310 RegClass = RC->getID(); 315 RegClass = TLI->getRepRegClassFor(VT)->getID(); [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCInstrInfo.cpp | 843 llvm_unreachable("Unknown regclass!"); [all...] |
/external/llvm/utils/TableGen/ |
CodeGenRegisters.cpp | 701 // Verify that all altorder members are regclass members. [all...] |
CodeGenDAGPatterns.cpp | [all...] |
/external/llvm/lib/Target/ARM/Disassembler/ |
ARMDisassembler.cpp | 570 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { [all...] |