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Searched
refs:RegIndex
(Results
1 - 10
of
10
) sorted by null
/external/llvm/lib/Target/R600/
AMDGPUInstrInfo.cpp
136
unsigned
RegIndex
= MI->getOperand(RegOpIdx).getImm();
138
unsigned Address = calculateIndirectAddress(
RegIndex
, Channel);
151
unsigned
RegIndex
= MI->getOperand(RegOpIdx).getImm();
153
unsigned Address = calculateIndirectAddress(
RegIndex
, Channel);
160
calculateIndirectAddress(
RegIndex
, Channel),
299
unsigned
RegIndex
;
301
for (
RegIndex
= 0, RegEnd = IndirectRC->getNumRegs();
RegIndex
!= RegEnd;
302
++
RegIndex
) {
303
if (IndirectRC->getRegister(
RegIndex
) == Reg
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all
...]
AMDGPUInstrInfo.h
150
/// \brief Calculate the "Indirect Address" for the given \p
RegIndex
and
155
/// address in this virtual address space that maps to the given \p
RegIndex
157
virtual unsigned calculateIndirectAddress(unsigned
RegIndex
,
SIInstrInfo.h
155
unsigned calculateIndirectAddress(unsigned
RegIndex
,
R600InstrInfo.h
216
unsigned calculateIndirectAddress(unsigned
RegIndex
,
R600InstrInfo.cpp
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...]
R600ISelLowering.cpp
597
int64_t
RegIndex
= cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
598
unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(
RegIndex
);
630
int64_t
RegIndex
= cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
631
unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(
RegIndex
);
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...]
SIInstrInfo.cpp
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...]
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
R600ISelLowering.cpp
99
int64_t
RegIndex
= MI->getOperand(1).getImm();
100
unsigned ConstantReg = AMDGPU::R600_CReg32RegClass.getRegister(
RegIndex
);
261
int64_t
RegIndex
= cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
262
unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(
RegIndex
);
282
int64_t
RegIndex
= cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
283
unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(
RegIndex
);
/external/mesa3d/src/gallium/drivers/radeon/
R600ISelLowering.cpp
99
int64_t
RegIndex
= MI->getOperand(1).getImm();
100
unsigned ConstantReg = AMDGPU::R600_CReg32RegClass.getRegister(
RegIndex
);
261
int64_t
RegIndex
= cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
262
unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(
RegIndex
);
282
int64_t
RegIndex
= cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
283
unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(
RegIndex
);
/external/llvm/lib/Target/Mips/AsmParser/
MipsAsmParser.cpp
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...]
Completed in 213 milliseconds