| /ndk/tests/device/issue42891-boost-1_52/jni/boost/boost/bind/ |
| bind_mf2_cc.hpp | 18 template<class Rt2, class R, class T,
20 _bi::bind_t<Rt2, _mfi::BOOST_BIND_MF_NAME(mf0)<R, T>, typename _bi::list_av_1<A1>::type>
21 BOOST_BIND(boost::type<Rt2>, R (BOOST_BIND_MF_CC T::*f) (), A1 a1)
25 return _bi::bind_t<Rt2, F, list_type>(F(f), list_type(a1));
28 template<class Rt2, class R, class T,
30 _bi::bind_t<Rt2, _mfi::BOOST_BIND_MF_NAME(cmf0)<R, T>, typename _bi::list_av_1<A1>::type>
31 BOOST_BIND(boost::type<Rt2>, R (BOOST_BIND_MF_CC T::*f) () const, A1 a1)
35 return _bi::bind_t<Rt2, F, list_type>(F(f), list_type(a1));
40 template<class Rt2, class R, class T,
43 _bi::bind_t<Rt2, _mfi::BOOST_BIND_MF_NAME(mf1)<R, T, B1>, typename _bi::list_av_2<A1, A2>::type
[all...] |
| /art/disassembler/ |
| disassembler_arm.cc | 559 ArmRegister Rt2 = Rd;
561 args << Rd << ", " << Rt << ", " << Rt2 << ", [" << Rn << "]";
563 Rt2.r == 13 || Rt2.r == 15 || Rn.r == 15 ||
564 Rd.r == Rn.r || Rd.r == Rt.r || Rd.r == Rt2.r) {
598 args << Rt << ", " << Rd /* Rt2 */ << ", [" << Rn << "]";
599 if (Rt.r == 13 || Rt.r == 15 || Rd.r == 13 /* Rt2 */ || Rd.r == 15 /* Rt2 */ ||
815 ArmRegister Rt2(instr, 16);
820 args << Rt << ", " << Rt2 << ", ";
[all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | [all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /external/llvm/test/MC/AArch64/ |
| arm64-diags.s | 155 ; Load pair instructions where Rt==Rt2 and writeback load/store instructions
156 ; where Rt==Rn or Rt2==Rn are unpredicatable.
185 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | [all...] |
| /external/llvm/test/MC/ARM/ |
| diagnostics.s | 298 @ Out of order Rt/Rt2 operands for ldrexd/strexd
372 @ Out of order Rt/Rt2 operands for ldrd
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/vixl/src/a64/ |
| assembler-a64.cc | 1025 const CPURegister& rt2,
1027 LoadStorePair(rt, rt2, src, LoadPairOpFor(rt, rt2));
1032 const CPURegister& rt2,
1034 LoadStorePair(rt, rt2, dst, StorePairOpFor(rt, rt2));
1039 const Register& rt2,
1042 LoadStorePair(rt, rt2, src, LDPSW_x);
1047 const CPURegister& rt2,
1050 // 'rt' and 'rt2' can only be aliased for stores
[all...] |
| constants-a64.h | 54 V_(Rt2, 14, 10, Bits) /* Load second dest / */ \
[all...] |
| assembler-a64.h | [all...] |
| simulator-a64.cc | 842 unsigned rt2 = instr->Rt2(); local
849 // 'rt' and 'rt2' can only be aliased for stores.
850 VIXL_ASSERT(((op & LoadStorePairLBit) == 0) || (rt != rt2));
855 set_wreg(rt2, MemoryRead32(address + kWRegSizeInBytes));
860 set_sreg(rt2, MemoryReadFP32(address + kSRegSizeInBytes));
865 set_xreg(rt2, MemoryRead64(address + kXRegSizeInBytes));
870 set_dreg(rt2, MemoryReadFP64(address + kDRegSizeInBytes));
875 set_xreg(rt2, ExtendValue(kXRegSize,
881 MemoryWrite32(address + kWRegSizeInBytes, wreg(rt2));
[all...] |
| /external/chromium_org/v8/src/arm64/ |
| constants-arm64.h | 130 V_(Rt2, 14, 10, Bits) /* Load second dest / */ \
[all...] |
| assembler-arm64.h | [all...] |
| assembler-arm64.cc | [all...] |
| simulator-arm64.cc | 1670 unsigned rt2 = instr->Rt2(); local
[all...] |
| /external/lldb/source/Plugins/Instruction/ARM/ |
| EmulateInstructionARM.cpp | [all...] |
