| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 154 case ISD::SDIV:
165 if (N->getOpcode() == ISD::SDIV) {
175 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
|
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 192 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence
194 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence
230 { ISD::SDIV, MVT::v32i8, 32*20 },
231 { ISD::SDIV, MVT::v16i16, 16*20 },
232 { ISD::SDIV, MVT::v8i32, 8*20 },
233 { ISD::SDIV, MVT::v4i64, 4*20 },
273 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence
275 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence
282 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41())
336 { ISD::SDIV, MVT::v16i8, 16*20 }
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 514 { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost},
518 { ISD::SDIV, MVT::v2i32, 2 * FunctionCallDivCost},
522 { ISD::SDIV, MVT::v4i16, ReciprocalDivCost},
526 { ISD::SDIV, MVT::v8i8, ReciprocalDivCost},
531 { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost},
535 { ISD::SDIV, MVT::v4i32, 4 * FunctionCallDivCost},
539 { ISD::SDIV, MVT::v8i16, 8 * FunctionCallDivCost},
543 { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost},
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 181 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
[all...] |
| SelectionDAGNodes.h | 57 case ISD::SDIV:
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.cpp | 89 case ISD::SDIV: return LowerSDIV(Op, DAG);
|
| AMDILISelLowering.cpp | 123 setOperationAction(ISD::SDIV, VT, Custom);
181 setOperationAction(ISD::SDIV, MVT::v2i64, Expand);
|
| /external/llvm/lib/Target/Mips/ |
| MipsCodeEmitter.cpp | 402 expandACCInstr(MI, MBB, Mips::SDIV);
|
| MipsSEISelLowering.cpp | 168 setOperationAction(ISD::SDIV, MVT::i32, Legal);
213 setOperationAction(ISD::SDIV, MVT::i64, Legal);
263 setOperationAction(ISD::SDIV, Ty, Legal);
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.cpp | 89 case ISD::SDIV: return LowerSDIV(Op, DAG);
|
| AMDILISelLowering.cpp | 123 setOperationAction(ISD::SDIV, VT, Custom);
181 setOperationAction(ISD::SDIV, MVT::v2i64, Expand);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 166 case ISD::SDIV: return "sdiv";
|
| FastISel.cpp | 412 // Transform "sdiv exact X, 8" -> "sra X, 3".
413 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &&
[all...] |
| LegalizeVectorOps.cpp | 15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
241 case ISD::SDIV:
[all...] |
| LegalizeVectorTypes.cpp | 114 case ISD::SDIV:
630 case ISD::SDIV:
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 154 setOperationAction(ISD::SDIV, MVT::i8, Expand);
160 setOperationAction(ISD::SDIV, MVT::i16, Expand);
[all...] |
| /external/pcre/dist/sljit/ |
| sljitNativeSPARC_common.c | 171 #define SDIV (OPC1(0x2) | OPC3(0x0f))
805 FAIL_IF(push_inst(compiler, (op == SLJIT_UDIV ? UDIV : SDIV) | D(SLJIT_R0) | S1(SLJIT_R0) | S2(SLJIT_R1), DR(SLJIT_R0)));
[all...] |
| sljitNativeARM_64.c | 110 #define SDIV 0x9ac00c00
[all...] |
| /external/chromium_org/v8/src/arm64/ |
| disasm-arm64.cc | 602 FORMAT(SDIV, "sdiv");
[all...] |
| constants-arm64.h | [all...] |
| /external/vixl/src/a64/ |
| disasm-a64.cc | 609 FORMAT(SDIV, "sdiv");
[all...] |
| constants-a64.h | 840 SDIV = SDIV_w,
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 248 setOperationAction(ISD::SDIV, VT, Expand);
304 setOperationAction(ISD::SDIV, VT, Expand);
534 case ISD::SDIV: return LowerSDIV(Op, DAG);
[all...] |
