| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 239 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
242 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
244 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
246 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
248 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
250 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
252 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
254 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
256 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
258 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }
[all...] |
| ARMISelLowering.cpp | 105 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
110 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
523 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
527 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 308 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
309 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
310 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
316 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
317 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
318 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
324 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 },
325 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
330 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
331 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 }
[all...] |
| AArch64ISelLowering.cpp | 189 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
190 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
191 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
348 setTargetDAGCombine(ISD::SINT_TO_FP);
417 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
426 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
428 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
430 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
432 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 538 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
539 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
540 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
541 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
547 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
548 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
549 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
550 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
621 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 },
622 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }
[all...] |
| X86ISelLowering.cpp | 327 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
345 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
347 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
348 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
353 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
355 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
358 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 372 SINT_TO_FP,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 305 case ISD::SINT_TO_FP:
346 case ISD::SINT_TO_FP:
[all...] |
| LegalizeFloatTypes.cpp | 101 case ISD::SINT_TO_FP:
581 bool Signed = N->getOpcode() == ISD::SINT_TO_FP;
[all...] |
| SelectionDAGDumper.cpp | 233 case ISD::SINT_TO_FP: return "sint_to_fp";
|
| LegalizeDAG.cpp | [all...] |
| LegalizeVectorTypes.cpp | 96 case ISD::SINT_TO_FP:
611 case ISD::SINT_TO_FP:
[all...] |
| FastISel.cpp | 224 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP,
[all...] |
| LegalizeIntegerTypes.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 527 SDValue fa = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ia);
530 SDValue fb = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ib);
|
| R600ISelLowering.cpp | 414 ConversionOp = ISD::SINT_TO_FP;
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 527 SDValue fa = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ia);
530 SDValue fb = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ib);
|
| R600ISelLowering.cpp | 414 ConversionOp = ISD::SINT_TO_FP;
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 104 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
105 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
111 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
356 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
363 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
374 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
494 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
599 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal)
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 301 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 278 setOperationAction(ISD::SINT_TO_FP, Ty, Legal);
[all...] |
